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体验新版 GitCode,发现更多精彩内容 >>
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41ef9492
编写于
6月 30, 2020
作者:
L
LinJiawei
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
Fix freelist bug
上级
8f60341d
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
18 addition
and
15 deletion
+18
-15
src/main/scala/xiangshan/backend/exu/Alu.scala
src/main/scala/xiangshan/backend/exu/Alu.scala
+0
-3
src/main/scala/xiangshan/backend/exu/Bru.scala
src/main/scala/xiangshan/backend/exu/Bru.scala
+0
-3
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+2
-0
src/main/scala/xiangshan/backend/rename/FreeList.scala
src/main/scala/xiangshan/backend/rename/FreeList.scala
+1
-1
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+15
-8
未找到文件。
src/main/scala/xiangshan/backend/exu/Alu.scala
浏览文件 @
41ef9492
...
...
@@ -109,9 +109,6 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) {
io
.
out
.
valid
:=
valid
io
.
out
.
bits
.
uop
<>
io
.
in
.
bits
.
uop
io
.
out
.
bits
.
data
:=
Mux
(
isJump
,
pcLatchSlot
,
aluRes
)
io
.
dmem
<>
DontCare
io
.
out
.
bits
.
debug
.
isMMIO
:=
DontCare
// FIXME: dont know how to do with it
XSDebug
(
io
.
in
.
valid
,
"In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n"
,
io
.
in
.
valid
,
io
.
in
.
ready
,
io
.
out
.
valid
,
io
.
out
.
ready
,
io
.
redirect
.
valid
,
io
.
redirect
.
bits
.
isException
,
redirectHit
,
io
.
redirect
.
bits
.
brTag
,
uop
.
brMask
)
...
...
src/main/scala/xiangshan/backend/exu/Bru.scala
浏览文件 @
41ef9492
...
...
@@ -57,9 +57,6 @@ class Bru extends Exu(FuType.bru.litValue(), writeFpRf = true, hasRedirect = tru
io
.
out
.
bits
.
uop
<>
io
.
in
.
bits
.
uop
io
.
out
.
bits
.
data
:=
res
io
.
dmem
<>
DontCare
io
.
out
.
bits
.
debug
.
isMMIO
:=
DontCare
// NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
XSDebug
(
io
.
in
.
valid
,
"In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n"
,
io
.
in
.
valid
,
io
.
in
.
ready
,
io
.
out
.
valid
,
io
.
out
.
ready
,
io
.
redirect
.
valid
,
io
.
redirect
.
bits
.
isException
,
redirectHit
,
io
.
redirect
.
bits
.
brTag
,
uop
.
brMask
)
...
...
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
41ef9492
...
...
@@ -38,6 +38,8 @@ abstract class Exu
val
hasRedirect
:
Boolean
=
false
)
extends
XSModule
{
val
io
=
IO
(
new
ExuIO
)
io
.
dmem
<>
DontCare
io
.
out
.
bits
.
debug
.
isMMIO
:=
false
.
B
}
class
Mul
extends
Exu
(
FuType
.
mul
.
litValue
())
with
NeedImpl
{
...
...
src/main/scala/xiangshan/backend/rename/FreeList.scala
浏览文件 @
41ef9492
...
...
@@ -75,8 +75,8 @@ class FreeList extends XSModule with HasFreeListConsts {
){
canAlloc
:=
!
empty
pdest
:=
freeList
(
headPtrNext
.
value
)
allocPtr
:=
headPtrNext
headPtrNext
=
headPtrNext
+
(
allocReq
&&
canAlloc
)
allocPtr
:=
headPtrNext
empty
=
isEmpty
(
headPtrNext
,
tailPtr
)
}
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
41ef9492
...
...
@@ -19,6 +19,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
val
scommit
=
Output
(
UInt
(
3.
W
))
})
val
numWbPorts
=
io
.
exeWbResults
.
length
val
microOp
=
Mem
(
RoqSize
,
new
MicroOp
)
// val brMask = Reg(Vec(RoqSize, UInt(BrqSize.W)))
val
valid
=
RegInit
(
VecInit
(
List
.
fill
(
RoqSize
)(
false
.
B
)))
...
...
@@ -66,9 +68,9 @@ class Roq(implicit val p: XSConfig) extends XSModule {
}
// Writeback
val
firedWriteback
=
VecInit
((
0
until
exuConfig
.
ExuCnt
).
map
(
io
.
exeWbResults
(
_
).
fire
())).
asUInt
val
firedWriteback
=
VecInit
((
0
until
numWbPorts
).
map
(
io
.
exeWbResults
(
_
).
fire
())).
asUInt
XSInfo
(
PopCount
(
firedWriteback
)
>
0.
U
,
"writebacked %d insts\n"
,
PopCount
(
firedWriteback
))
for
(
i
<-
0
until
exuConfig
.
ExuCnt
){
for
(
i
<-
0
until
numWbPorts
){
when
(
io
.
exeWbResults
(
i
).
fire
()){
writebacked
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
)
:=
true
.
B
exuData
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
)
:=
io
.
exeWbResults
(
i
).
bits
.
data
...
...
@@ -96,7 +98,17 @@ class Roq(implicit val p: XSConfig) extends XSModule {
archRF
(
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
ldest
)
:=
exuData
(
ringBufferTail
+
i
.
U
)
}
// for difftest
when
(
io
.
commits
(
i
).
valid
){
valid
(
ringBufferTail
+
i
.
U
)
:=
false
.
B
}
XSInfo
(
io
.
commits
(
i
).
valid
,
"retired pc %x wen %d ldst %d data %x\n"
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
,
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
rfWen
,
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
ldest
,
exuData
(
ringBufferTail
+
i
.
U
))
XSInfo
(
io
.
commits
(
i
).
valid
,
"retired pc %x wen %d ldst %d data %x\n"
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
,
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
rfWen
,
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
ldest
,
exuData
(
ringBufferTail
+
i
.
U
)
)
XSInfo
(
io
.
commits
(
i
).
valid
&&
exuDebug
(
ringBufferTail
+
i
.
U
).
isMMIO
,
"difftest skiped pc0x%x\n"
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
)
}.
otherwise
{
//state === s_walk
io
.
commits
(
i
).
valid
:=
valid
(
ringBufferWalk
+
i
.
U
)
&&
shouldWalkVec
(
i
)
io
.
commits
(
i
).
bits
.
uop
:=
microOp
(
ringBufferWalk
+
i
.
U
)
...
...
@@ -125,11 +137,6 @@ class Roq(implicit val p: XSConfig) extends XSModule {
val
retireCounter
=
Mux
(
state
===
s_idle
,
PopCount
(
validCommit
),
0.
U
)
XSInfo
(
retireCounter
>
0.
U
,
"retired %d insts\n"
,
retireCounter
)
for
(
i
<-
0
until
CommitWidth
)
{
XSInfo
(
io
.
commits
(
i
).
valid
,
"retired pc at commmit(%d) is: %d 0x%x\n"
,
i
.
U
,
ringBufferTail
+
i
.
U
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
)
XSInfo
(
io
.
commits
(
i
).
valid
&&
exuDebug
(
ringBufferTail
+
i
.
U
).
isMMIO
,
"difftest skiped pc0x%x\n"
,
microOp
(
ringBufferTail
+
i
.
U
).
cf
.
pc
)
}
// commit store to lsu
val
validScommit
=
WireInit
(
VecInit
((
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
(
i
).
valid
&&
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
fuType
===
FuType
.
ldu
&&
microOp
(
ringBufferTail
+
i
.
U
).
ctrl
.
fuOpType
(
3
))))
//FIXIT
...
...
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