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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
f7f707b0
编写于
1月 26, 2021
作者:
L
LinJiawei
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电子邮件补丁
差异文件
fix perf print, enable perf by default
上级
629b6073
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
6 addition
and
6 deletion
+6
-6
src/main/scala/top/Parameters.scala
src/main/scala/top/Parameters.scala
+1
-1
src/main/scala/utils/LogUtils.scala
src/main/scala/utils/LogUtils.scala
+1
-3
src/main/scala/xiangshan/backend/CtrlBlock.scala
src/main/scala/xiangshan/backend/CtrlBlock.scala
+2
-0
src/main/scala/xiangshan/backend/ftq/Ftq.scala
src/main/scala/xiangshan/backend/ftq/Ftq.scala
+2
-2
未找到文件。
src/main/scala/top/Parameters.scala
浏览文件 @
f7f707b0
...
...
@@ -22,7 +22,7 @@ case class Parameters
object
Parameters
{
val
dualCoreParameters
=
Parameters
(
socParameters
=
SoCParameters
(
NumCores
=
2
))
val
simParameters
=
Parameters
(
envParameters
=
EnviromentParameters
(
FPGAPlatform
=
false
))
// sim only, disable log
val
debugParameters
=
Parameters
(
envParameters
=
simParameters
.
envParameters
.
copy
(
EnableDebug
=
true
))
// open log
val
debugParameters
=
Parameters
(
envParameters
=
simParameters
.
envParameters
.
copy
(
EnableDebug
=
true
,
EnablePerfDebug
=
true
))
// open log
val
simDualCoreParameters
=
Parameters
(
socParameters
=
SoCParameters
(
NumCores
=
2
),
envParameters
=
EnviromentParameters
(
FPGAPlatform
=
false
))
val
debugDualCoreParameters
=
Parameters
(
socParameters
=
SoCParameters
(
NumCores
=
2
),
envParameters
=
simParameters
.
envParameters
.
copy
(
EnableDebug
=
true
))
...
...
src/main/scala/utils/LogUtils.scala
浏览文件 @
f7f707b0
...
...
@@ -108,16 +108,14 @@ object XSPerf {
val
next_counter
=
WireInit
(
0.
U
(
64.
W
))
val
logTimestamp
=
WireInit
(
0.
U
(
64.
W
))
val
enableDebug
=
Parameters
.
get
.
envParameters
.
EnableDebug
val
logEnable
=
WireInit
(
false
.
B
)
next_counter
:=
counter
+
perfCnt
counter
:=
next_counter
if
(
enableDebug
)
{
ExcitingUtils
.
addSink
(
logEnable
,
"DISPLAY_LOG_ENABLE"
)
ExcitingUtils
.
addSink
(
logTimestamp
,
"logTimestamp"
)
val
printCond
=
if
(
intervalBits
==
0
)
true
.
B
else
(
log
Enable
&&
log
Timestamp
(
intervalBits
-
1
,
0
)
===
0.
U
)
else
(
logTimestamp
(
intervalBits
-
1
,
0
)
===
0.
U
)
when
(
printCond
)
{
// TODO: Need print when program exit?
if
(
acc
)
{
XSLog
(
XSLogLevel
.
PERF
)(
true
,
true
.
B
,
p
"$perfName, $next_counter\n"
)
...
...
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @
f7f707b0
...
...
@@ -97,6 +97,8 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper {
redirect
})
XSDebug
(
oldestExuOut
.
valid
,
p
"exuMispredict: ${Binary(Cat(io.exuMispredict.map(_.valid)))}\n"
)
val
s1_isJump
=
RegNext
(
jumpIsOlder
,
init
=
false
.
B
)
val
s1_jumpTarget
=
RegEnable
(
jumpOut
.
bits
.
redirect
.
cfiUpdate
.
target
,
jumpOut
.
valid
)
val
s1_imm12_reg
=
RegEnable
(
oldestExuOut
.
bits
.
uop
.
ctrl
.
imm
(
11
,
0
),
oldestExuOut
.
valid
)
...
...
src/main/scala/xiangshan/backend/ftq/Ftq.scala
浏览文件 @
f7f707b0
...
...
@@ -177,6 +177,6 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
XSPerf
(
"mispredictRedirectAcc"
,
io
.
redirect
.
valid
&&
RedirectLevel
.
flushAfter
===
io
.
redirect
.
bits
.
level
,
acc
=
true
)
XSPerf
(
"replayRedirectAcc"
,
io
.
redirect
.
valid
&&
RedirectLevel
.
flushItself
(
io
.
redirect
.
bits
.
level
),
acc
=
true
)
XSDebug
(
io
.
commit_ftqEntry
.
valid
,
io
.
commit_ftqEntry
.
bits
.
toPrintable
)
XSDebug
(
io
.
enq
.
fire
(),
io
.
enq
.
bits
.
toPrintable
)
XSDebug
(
io
.
commit_ftqEntry
.
valid
,
p
"ftq commit: ${io.commit_ftqEntry.bits}"
)
XSDebug
(
io
.
enq
.
fire
(),
p
"ftq enq: ${io.enq.bits}"
)
}
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