LSU: avoid potential stuck caused by illegal inst

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -104,7 +104,7 @@ class LoadUnit_S1 extends XSModule {
   val s1_uop = io.in.bits.uop
   val s1_paddr = io.in.bits.paddr
   val s1_tlb_miss = io.in.bits.tlbMiss
-  val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr)
+  val s1_mmio = !s1_tlb_miss && AddressSpace.isMMIO(s1_paddr) && !io.out.bits.uop.cf.exceptionVec.asUInt.orR
   val s1_mask = io.in.bits.mask
 
   io.out.bits := io.in.bits // forwardXX field will be updated in s1