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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
f22cf846
编写于
7月 19, 2022
作者:
J
Jenius
提交者:
Lingrui98
11月 09, 2022
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
ftq: copy bpu bypass write registers
* FtqToICache add bypass write signal and use bypass signal
上级
2da4ac8c
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
34 addition
and
35 deletion
+34
-35
src/main/scala/xiangshan/frontend/FrontendBundle.scala
src/main/scala/xiangshan/frontend/FrontendBundle.scala
+11
-5
src/main/scala/xiangshan/frontend/NewFtq.scala
src/main/scala/xiangshan/frontend/NewFtq.scala
+12
-22
src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
...main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
+11
-8
未找到文件。
src/main/scala/xiangshan/frontend/FrontendBundle.scala
浏览文件 @
f22cf846
...
@@ -59,13 +59,19 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICache
...
@@ -59,13 +59,19 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICache
}
}
}
}
class
Ftq
ToICacheRequestBundle
(
implicit
p
:
Parameters
)
extends
XSBundle
with
HasICacheParameters
{
class
Ftq
ICacheInfo
(
implicit
p
:
Parameters
)
extends
XSBundle
with
HasICacheParameters
{
val
startAddr
=
UInt
(
VAddrBits
.
W
)
val
startAddr
=
UInt
(
VAddrBits
.
W
)
val
nextlineStart
=
UInt
(
VAddrBits
.
W
)
val
nextlineStart
=
UInt
(
VAddrBits
.
W
)
def
crossCacheline
=
startAddr
(
blockOffBits
-
1
)
===
1.
U
def
crossCacheline
=
startAddr
(
blockOffBits
-
1
)
===
1.
U
}
class
FtqToICacheRequestBundle
(
implicit
p
:
Parameters
)
extends
XSBundle
with
HasICacheParameters
{
val
pcMemRead
=
new
FtqICacheInfo
val
bpuBypassWrite
=
Vec
(
4
,
new
FtqICacheInfo
)
val
bypassSelect
=
Bool
()
def
fromFtqPcBundle
(
b
:
Ftq_RF_Components
)
=
{
def
fromFtqPcBundle
(
b
:
Ftq_RF_Components
)
=
{
this
.
startAddr
:=
b
.
startAddr
this
.
pcMemRead
.
startAddr
:=
b
.
startAddr
this
.
nextlineStart
:=
b
.
nextLineAddr
this
.
pcMemRead
.
nextlineStart
:=
b
.
nextLineAddr
this
this
}
}
}
}
...
...
src/main/scala/xiangshan/frontend/NewFtq.scala
浏览文件 @
f22cf846
...
@@ -607,7 +607,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -607,7 +607,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
// ****************************************************************
// ****************************************************************
// **************************** to ifu ****************************
// **************************** to ifu ****************************
// ****************************************************************
// ****************************************************************
val
bpu_in_bypass_buf
=
RegEnable
(
ftq_pc_mem
.
io
.
wdata
,
enable
=
bpu_in_fire
)
// 0 for ifu, and 1-4 for ICache
val
bpu_in_bypass_buf
=
VecInit
(
Seq
.
fill
(
5
)(
RegEnable
(
ftq_pc_mem
.
io
.
wdata
,
enable
=
bpu_in_fire
)))
val
bpu_in_bypass_ptr
=
RegNext
(
bpu_in_resp_ptr
)
val
bpu_in_bypass_ptr
=
RegNext
(
bpu_in_resp_ptr
)
val
last_cycle_to_ifu_fire
=
RegNext
(
io
.
toIfu
.
req
.
fire
)
val
last_cycle_to_ifu_fire
=
RegNext
(
io
.
toIfu
.
req
.
fire
)
...
@@ -626,16 +627,14 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -626,16 +627,14 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
io
.
toIfu
.
req
.
bits
.
ftqIdx
:=
ifuPtr
io
.
toIfu
.
req
.
bits
.
ftqIdx
:=
ifuPtr
val
toICachePcBundle
=
Wire
(
new
Ftq_RF_Components
)
val
toICachePcBundle
=
Wire
Init
(
ftq_pc_mem
.
io
.
ifuPtr_rdata
)
val
toIfuPcBundle
=
Wire
(
new
Ftq_RF_Components
)
val
toIfuPcBundle
=
Wire
(
new
Ftq_RF_Components
)
val
entry_is_to_send
=
WireInit
(
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
)
val
entry_is_to_send
=
WireInit
(
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
)
val
entry_next_addr
=
WireInit
(
update_target
(
ifuPtr
.
value
))
val
entry_next_addr
=
WireInit
(
update_target
(
ifuPtr
.
value
))
val
entry_ftq_offset
=
WireInit
(
cfiIndex_vec
(
ifuPtr
.
value
))
val
entry_ftq_offset
=
WireInit
(
cfiIndex_vec
(
ifuPtr
.
value
))
when
(
last_cycle_bpu_in
&&
bpu_in_bypass_ptr
===
ifuPtr
)
{
when
(
last_cycle_bpu_in
&&
bpu_in_bypass_ptr
===
ifuPtr
)
{
toIfuPcBundle
:=
bpu_in_bypass_buf
toIfuPcBundle
:=
bpu_in_bypass_buf
.
head
toICachePcBundle
:=
ftq_pc_mem
.
io
.
wdata
entry_is_to_send
:=
true
.
B
entry_is_to_send
:=
true
.
B
entry_next_addr
:=
last_cycle_update_target
entry_next_addr
:=
last_cycle_update_target
entry_ftq_offset
:=
last_cycle_cfiIndex
entry_ftq_offset
:=
last_cycle_cfiIndex
...
@@ -646,21 +645,23 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -646,21 +645,23 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
RegNext
(
last_cycle_bpu_in
&&
bpu_in_bypass_ptr
===
(
ifuPtrPlus1
))
// reduce potential bubbles
RegNext
(
last_cycle_bpu_in
&&
bpu_in_bypass_ptr
===
(
ifuPtrPlus1
))
// reduce potential bubbles
}.
otherwise
{
}.
otherwise
{
toIfuPcBundle
:=
RegNext
(
ftq_pc_mem
.
io
.
ifuPtr_rdata
)
toIfuPcBundle
:=
RegNext
(
ftq_pc_mem
.
io
.
ifuPtr_rdata
)
toICachePcBundle
:=
ftq_pc_mem
.
io
.
ifuPtr_rdata
//
toICachePcBundle := ftq_pc_mem.io.ifuPtr_rdata
entry_is_to_send
:=
RegNext
(
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
)
entry_is_to_send
:=
RegNext
(
entry_fetch_status
(
ifuPtr
.
value
)
===
f_to_send
)
}
}
io
.
toIfu
.
req
.
valid
:=
entry_is_to_send
&&
ifuPtr
=/=
bpuPtr
io
.
toIfu
.
req
.
valid
:=
entry_is_to_send
&&
ifuPtr
=/=
bpuPtr
io
.
toIfu
.
req
.
bits
.
nextStartAddr
:=
entry_next_addr
io
.
toIfu
.
req
.
bits
.
nextStartAddr
:=
entry_next_addr
io
.
toIfu
.
req
.
bits
.
ftqOffset
:=
entry_ftq_offset
io
.
toIfu
.
req
.
bits
.
ftqOffset
:=
entry_ftq_offset
io
.
toIfu
.
req
.
bits
.
fromFtqPcBundle
(
toIfuPcBundle
)
io
.
toIfu
.
req
.
bits
.
fromFtqPcBundle
(
toIfuPcBundle
)
<<<<<<<
HEAD
=======
io
.
toICache
.
req
.
valid
:=
entry_is_to_send
&&
ifuPtr
=/=
bpuPtr
io
.
toICache
.
req
.
valid
:=
entry_is_to_send
&&
ifuPtr
=/=
bpuPtr
io
.
toICache
.
req
.
bits
.
fromFtqPcBundle
(
toICachePcBundle
)
io
.
toICache
.
req
.
bits
.
fromFtqPcBundle
(
toICachePcBundle
)
>>>>>>>
3d
9
e78c83
([
WIP
]
FTQ
:
add
icache
req
port
)
io
.
toICache
.
req
.
bits
.
bypassSelect
:=
last_cycle_bpu_in
&&
bpu_in_bypass_ptr
===
ifuPtr
io
.
toICache
.
req
.
bits
.
bpuBypassWrite
.
zipWithIndex
.
map
{
case
(
bypassWrtie
,
i
)
=>
bypassWrtie
.
startAddr
:=
bpu_in_bypass_buf
.
tail
(
i
).
startAddr
bypassWrtie
.
nextlineStart
:=
bpu_in_bypass_buf
.
tail
(
i
).
nextLineAddr
}
// when fall through is smaller in value than start address, there must be a false hit
// when fall through is smaller in value than start address, there must be a false hit
when
(
toIfuPcBundle
.
fallThruError
&&
entry_hit_status
(
ifuPtr
.
value
)
===
h_hit
)
{
when
(
toIfuPcBundle
.
fallThruError
&&
entry_hit_status
(
ifuPtr
.
value
)
===
h_hit
)
{
when
(
io
.
toIfu
.
req
.
fire
&&
when
(
io
.
toIfu
.
req
.
fire
&&
...
@@ -757,22 +758,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
...
@@ -757,22 +758,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
// **********************************************************************
// **********************************************************************
// ***************************** to backend *****************************
// ***************************** to backend *****************************
// **********************************************************************
// **********************************************************************
<<<<<<<
HEAD
// to backend pc mem / target
// to backend pc mem / target
io
.
toBackend
.
pc_mem_wen
:=
RegNext
(
last_cycle_bpu_in
)
io
.
toBackend
.
pc_mem_wen
:=
RegNext
(
last_cycle_bpu_in
)
io
.
toBackend
.
pc_mem_waddr
:=
RegNext
(
last_cycle_bpu_in_idx
)
io
.
toBackend
.
pc_mem_waddr
:=
RegNext
(
last_cycle_bpu_in_idx
)
io
.
toBackend
.
pc_mem_wdata
:=
RegNext
(
bpu_in_bypass_buf
)
io
.
toBackend
.
pc_mem_wdata
:=
RegNext
(
bpu_in_bypass_buf
)
io
.
toBackend
.
target
:=
RegNext
(
last_cycle_update_target
)
io
.
toBackend
.
target
:=
RegNext
(
last_cycle_update_target
)
=======
// pc reads
for
((
req
,
i
)
<-
io
.
toBackend
.
pc_reads
.
zipWithIndex
)
{
ftq_pc_mem
.
io
.
other_raddrs
(
i
)
:=
req
.
ptr
.
value
req
.
data
:=
ftq_pc_mem
.
io
.
other_rdatas
(
i
).
getPc
(
RegNext
(
req
.
offset
))
}
// target read
io
.
toBackend
.
target_read
.
data
:=
RegNext
(
update_target
(
io
.
toBackend
.
target_read
.
ptr
.
value
))
>>>>>>>
8973
c7ae8
([
WIP
]
ftq
:
read
ftq_pc_mem
one
cycle
ahead
,
reqs
to
be
copied
)
// *******************************************************************************
// *******************************************************************************
// **************************** redirect from backend ****************************
// **************************** redirect from backend ****************************
...
...
src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
浏览文件 @
f22cf846
...
@@ -24,7 +24,7 @@ import xiangshan._
...
@@ -24,7 +24,7 @@ import xiangshan._
import
xiangshan.cache.mmu._
import
xiangshan.cache.mmu._
import
utils._
import
utils._
import
xiangshan.backend.fu.
{
PMPReqBundle
,
PMPRespBundle
}
import
xiangshan.backend.fu.
{
PMPReqBundle
,
PMPRespBundle
}
import
xiangshan.frontend.
{
FtqToICacheRequestBundle
}
import
xiangshan.frontend.
{
Ftq
ICacheInfo
,
Ftq
ToICacheRequestBundle
}
class
ICacheMainPipeReq
(
implicit
p
:
Parameters
)
extends
ICacheBundle
class
ICacheMainPipeReq
(
implicit
p
:
Parameters
)
extends
ICacheBundle
{
{
...
@@ -121,9 +121,12 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
...
@@ -121,9 +121,12 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
io
.
itlb
.
foreach
(
_
.
req_kill
:=
false
.
B
)
io
.
itlb
.
foreach
(
_
.
req_kill
:=
false
.
B
)
//Ftq RegNext Register
//Ftq RegNext Register
val
ftqReqReg
=
Reg
(
Vec
(
partWayNum
,
new
FtqToICacheRequestBundle
))
val
pcMemReadReg
=
Reg
(
Vec
(
partWayNum
,
new
FtqICacheInfo
))
ftqReqReg
.
map
(
_
:=
fromFtq
.
bits
)
val
fromFtqReq
=
Wire
(
Vec
(
partWayNum
,
new
FtqICacheInfo
))
dontTouch
(
ftqReqReg
)
pcMemReadReg
.
map
(
_
:=
fromFtq
.
bits
.
pcMemRead
)
fromFtqReq
.
zipWithIndex
.
map
{
case
(
req
,
i
)
=>
req
:=
Mux
(
fromFtq
.
bits
.
bypassSelect
,
fromFtq
.
bits
.
bpuBypassWrite
(
i
),
pcMemReadReg
(
i
)
)}
dontTouch
(
pcMemReadReg
)
/** pipeline control signal */
/** pipeline control signal */
val
s1_ready
,
s2_ready
=
Wire
(
Bool
())
val
s1_ready
,
s2_ready
=
Wire
(
Bool
())
...
@@ -145,10 +148,10 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
...
@@ -145,10 +148,10 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
/** s0 control */
/** s0 control */
val
s0_valid
=
fromFtq
.
valid
val
s0_valid
=
fromFtq
.
valid
val
s0_req_vaddr
=
(
0
until
partWayNum
).
map
(
i
=>
VecInit
(
Seq
(
f
tqReqReg
(
i
).
startAddr
,
ftqReqReg
(
i
).
nextlineStart
)))
//VecInit(fromIFU.map(_.bits.vaddr
))
val
s0_req_vaddr
=
(
0
until
partWayNum
).
map
(
i
=>
VecInit
(
Seq
(
f
romFtqReq
(
i
).
startAddr
,
fromFtqReq
(
i
).
nextlineStart
)
))
val
s0_req_vsetIdx
=
(
0
until
partWayNum
).
map
(
i
=>
VecInit
(
s0_req_vaddr
(
i
).
map
(
get_idx
(
_
))))
//VecInit(fromIFU.map(_.bits.vsetIdx))
val
s0_req_vsetIdx
=
(
0
until
partWayNum
).
map
(
i
=>
VecInit
(
s0_req_vaddr
(
i
).
map
(
get_idx
(
_
))))
val
s0_only_first
=
(
0
until
partWayNum
).
map
(
i
=>
fromFtq
.
valid
&&
!
f
tqReqReg
(
i
).
crossCacheline
)
//fromFtq.valid && !ftqReqReg.crossCacheline
val
s0_only_first
=
(
0
until
partWayNum
).
map
(
i
=>
fromFtq
.
valid
&&
!
f
romFtqReq
(
i
).
crossCacheline
)
val
s0_double_line
=
(
0
until
partWayNum
).
map
(
i
=>
fromFtq
.
valid
&&
f
tqReqReg
(
i
).
crossCacheline
)
val
s0_double_line
=
(
0
until
partWayNum
).
map
(
i
=>
fromFtq
.
valid
&&
f
romFtqReq
(
i
).
crossCacheline
)
val
s0_final_valid
=
s0_valid
val
s0_final_valid
=
s0_valid
val
s0_final_vaddr
=
s0_req_vaddr
val
s0_final_vaddr
=
s0_req_vaddr
...
...
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