diff --git a/src/main/scala/xiangshan/frontend/FrontendBundle.scala b/src/main/scala/xiangshan/frontend/FrontendBundle.scala index 168f9f2ade9c4000973df3e8da3454d08e595e0c..baa0b97d4ce13885d4abfbb23f33039e6c9be475 100644 --- a/src/main/scala/xiangshan/frontend/FrontendBundle.scala +++ b/src/main/scala/xiangshan/frontend/FrontendBundle.scala @@ -59,13 +59,19 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICache } } -class FtqToICacheRequestBundle(implicit p: Parameters)extends XSBundle with HasICacheParameters{ - val startAddr = UInt(VAddrBits.W) - val nextlineStart = UInt(VAddrBits.W) +class FtqICacheInfo(implicit p: Parameters)extends XSBundle with HasICacheParameters{ + val startAddr = UInt(VAddrBits.W) + val nextlineStart = UInt(VAddrBits.W) def crossCacheline = startAddr(blockOffBits - 1) === 1.U +} + +class FtqToICacheRequestBundle(implicit p: Parameters)extends XSBundle with HasICacheParameters{ + val pcMemRead = new FtqICacheInfo + val bpuBypassWrite = Vec(4, new FtqICacheInfo) + val bypassSelect = Bool() def fromFtqPcBundle(b: Ftq_RF_Components) = { - this.startAddr := b.startAddr - this.nextlineStart := b.nextLineAddr + this.pcMemRead.startAddr := b.startAddr + this.pcMemRead.nextlineStart := b.nextLineAddr this } } diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala index 7c890bc4c094fd56fb5cd523f1b54d6fd7e84ed8..4c24254874f149e9468174a22b6a24c8a21354ed 100644 --- a/src/main/scala/xiangshan/frontend/NewFtq.scala +++ b/src/main/scala/xiangshan/frontend/NewFtq.scala @@ -607,7 +607,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe // **************************************************************** // **************************** to ifu **************************** // **************************************************************** - val bpu_in_bypass_buf = RegEnable(ftq_pc_mem.io.wdata, enable=bpu_in_fire) + // 0 for ifu, and 1-4 for ICache + val bpu_in_bypass_buf = VecInit(Seq.fill(5)(RegEnable(ftq_pc_mem.io.wdata, enable=bpu_in_fire))) val bpu_in_bypass_ptr = RegNext(bpu_in_resp_ptr) val last_cycle_to_ifu_fire = RegNext(io.toIfu.req.fire) @@ -626,16 +627,14 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe io.toIfu.req.bits.ftqIdx := ifuPtr - val toICachePcBundle = Wire(new Ftq_RF_Components) + val toICachePcBundle = WireInit(ftq_pc_mem.io.ifuPtr_rdata) val toIfuPcBundle = Wire(new Ftq_RF_Components) val entry_is_to_send = WireInit(entry_fetch_status(ifuPtr.value) === f_to_send) val entry_next_addr = WireInit(update_target(ifuPtr.value)) val entry_ftq_offset = WireInit(cfiIndex_vec(ifuPtr.value)) - when (last_cycle_bpu_in && bpu_in_bypass_ptr === ifuPtr) { - toIfuPcBundle := bpu_in_bypass_buf - toICachePcBundle := ftq_pc_mem.io.wdata + toIfuPcBundle := bpu_in_bypass_buf.head entry_is_to_send := true.B entry_next_addr := last_cycle_update_target entry_ftq_offset := last_cycle_cfiIndex @@ -646,21 +645,23 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe RegNext(last_cycle_bpu_in && bpu_in_bypass_ptr === (ifuPtrPlus1)) // reduce potential bubbles }.otherwise { toIfuPcBundle := RegNext(ftq_pc_mem.io.ifuPtr_rdata) - toICachePcBundle := ftq_pc_mem.io.ifuPtr_rdata + //toICachePcBundle := ftq_pc_mem.io.ifuPtr_rdata entry_is_to_send := RegNext(entry_fetch_status(ifuPtr.value) === f_to_send) } - + io.toIfu.req.valid := entry_is_to_send && ifuPtr =/= bpuPtr io.toIfu.req.bits.nextStartAddr := entry_next_addr io.toIfu.req.bits.ftqOffset := entry_ftq_offset io.toIfu.req.bits.fromFtqPcBundle(toIfuPcBundle) -<<<<<<< HEAD - -======= io.toICache.req.valid := entry_is_to_send && ifuPtr =/= bpuPtr io.toICache.req.bits.fromFtqPcBundle(toICachePcBundle) ->>>>>>> 3d9e78c83 ([WIP]FTQ: add icache req port) + io.toICache.req.bits.bypassSelect := last_cycle_bpu_in && bpu_in_bypass_ptr === ifuPtr + io.toICache.req.bits.bpuBypassWrite.zipWithIndex.map{case(bypassWrtie, i) => + bypassWrtie.startAddr := bpu_in_bypass_buf.tail(i).startAddr + bypassWrtie.nextlineStart := bpu_in_bypass_buf.tail(i).nextLineAddr + } + // when fall through is smaller in value than start address, there must be a false hit when (toIfuPcBundle.fallThruError && entry_hit_status(ifuPtr.value) === h_hit) { when (io.toIfu.req.fire && @@ -757,22 +758,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe // ********************************************************************** // ***************************** to backend ***************************** // ********************************************************************** -<<<<<<< HEAD // to backend pc mem / target io.toBackend.pc_mem_wen := RegNext(last_cycle_bpu_in) io.toBackend.pc_mem_waddr := RegNext(last_cycle_bpu_in_idx) io.toBackend.pc_mem_wdata := RegNext(bpu_in_bypass_buf) io.toBackend.target := RegNext(last_cycle_update_target) -======= - - // pc reads - for ((req, i) <- io.toBackend.pc_reads.zipWithIndex) { - ftq_pc_mem.io.other_raddrs(i) := req.ptr.value - req.data := ftq_pc_mem.io.other_rdatas(i).getPc(RegNext(req.offset)) - } - // target read - io.toBackend.target_read.data := RegNext(update_target(io.toBackend.target_read.ptr.value)) ->>>>>>> 8973c7ae8 ([WIP]ftq: read ftq_pc_mem one cycle ahead, reqs to be copied) // ******************************************************************************* // **************************** redirect from backend **************************** diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala index b087c7d6acd6af2dab3e12869484676990176a4d..01e65da6351d3a31a6a2101b99c17209f928dca4 100644 --- a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala +++ b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala @@ -24,7 +24,7 @@ import xiangshan._ import xiangshan.cache.mmu._ import utils._ import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} -import xiangshan.frontend.{FtqToICacheRequestBundle} +import xiangshan.frontend.{FtqICacheInfo, FtqToICacheRequestBundle} class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle { @@ -121,9 +121,12 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule io.itlb.foreach(_.req_kill := false.B) //Ftq RegNext Register - val ftqReqReg = Reg(Vec(partWayNum, new FtqToICacheRequestBundle)) - ftqReqReg.map(_ := fromFtq.bits) - dontTouch(ftqReqReg) + val pcMemReadReg = Reg(Vec(partWayNum, new FtqICacheInfo)) + val fromFtqReq = Wire(Vec(partWayNum, new FtqICacheInfo)) + pcMemReadReg.map( _ := fromFtq.bits.pcMemRead) + + fromFtqReq.zipWithIndex.map{case(req,i) => req := Mux(fromFtq.bits.bypassSelect, fromFtq.bits.bpuBypassWrite(i), pcMemReadReg(i) )} + dontTouch(pcMemReadReg) /** pipeline control signal */ val s1_ready, s2_ready = Wire(Bool()) @@ -145,10 +148,10 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule /** s0 control */ val s0_valid = fromFtq.valid - val s0_req_vaddr = (0 until partWayNum).map(i => VecInit(Seq(ftqReqReg(i).startAddr, ftqReqReg(i).nextlineStart))) //VecInit(fromIFU.map(_.bits.vaddr)) - val s0_req_vsetIdx = (0 until partWayNum).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) //VecInit(fromIFU.map(_.bits.vsetIdx)) - val s0_only_first = (0 until partWayNum).map(i => fromFtq.valid && !ftqReqReg(i).crossCacheline) //fromFtq.valid && !ftqReqReg.crossCacheline - val s0_double_line = (0 until partWayNum).map(i => fromFtq.valid && ftqReqReg(i).crossCacheline) + val s0_req_vaddr = (0 until partWayNum).map(i => VecInit(Seq(fromFtqReq(i).startAddr, fromFtqReq(i).nextlineStart))) + val s0_req_vsetIdx = (0 until partWayNum).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) + val s0_only_first = (0 until partWayNum).map(i => fromFtq.valid && !fromFtqReq(i).crossCacheline) + val s0_double_line = (0 until partWayNum).map(i => fromFtq.valid && fromFtqReq(i).crossCacheline) val s0_final_valid = s0_valid val s0_final_vaddr = s0_req_vaddr