Merge pull request #257 from RISCVERS/fix-module-level

Fix fflags bug

.github/workflows/emu.yml

@@ -45,7 +45,7 @@ jobs:
           exit $ret
       - name: Run riscv-tests
         run: |
-          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run 2> /dev/null
+          make -C $RVTEST_HOME/isa/ SUITES+=rv64ui SUITES+=rv64um SUITES+=rv64ua SUITES+=rv64uf SUITES+=rv64ud NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME noop_run 2> /dev/null
       - name: Run microbench
         run: |
           make -C $AM_HOME/apps/microbench ARCH=riscv64-noop AM_HOME=$AM_HOME NEMU_HOME=$NEMU_HOME NOOP_HOME=$NOOP_HOME mainargs=test run 2> /dev/null

src/main/scala/xiangshan/Bundle.scala

@@ -143,8 +143,8 @@ class CtrlSignals extends XSBundle {
   val rfWen = Bool()
   val fpWen = Bool()
   val isXSTrap = Bool()
-  val noSpecExec = Bool()  // This inst can not be speculated
-  val isBlocked  = Bool()  // This inst requires pipeline to be blocked
+  val noSpecExec = Bool()  // wait forward
+  val blockBackward  = Bool()  // block backward
   val flushPipe  = Bool()  // This inst will flush all the pipe when commit, like exception but can commit
   val isRVF = Bool()
   val imm = UInt(XLEN.W)

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -182,7 +182,21 @@ class Decoder extends XSModule with HasInstrType {
   when(io.out.ctrl.isXSTrap){
     io.out.ctrl.lsrc1 := 10.U // a0
   }
-  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou || io.out.ctrl.fuType===FuType.fence/*noSpecExec make it sent to alu0,for roq is empty*/
+
+  /*noSpecExec make it sent to alu0,for roq is empty*/
+  io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap ||
+    io.out.ctrl.fuType===FuType.csr ||
+    io.out.ctrl.fuType===FuType.mou ||
+    io.out.ctrl.fuType===FuType.fence
+
+  //                           fflags    zero csrrs rd    csr
+  val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === io.in.instr
+
+  io.out.ctrl.blockBackward := io.out.ctrl.isXSTrap ||
+    (io.out.ctrl.fuType===FuType.csr && !isFrflags) ||
+    io.out.ctrl.fuType===FuType.mou ||
+    io.out.ctrl.fuType===FuType.fence
+
   io.out.ctrl.flushPipe := io.out.ctrl.fuType===FuType.fence
 
   io.out.ctrl.isRVF := instr(26, 25) === 0.U
@@ -193,5 +207,5 @@ class Decoder extends XSModule with HasInstrType {
   XSDebug("out: src1Type=%b src2Type=%b src3Type=%b lsrc1=%d lsrc2=%d lsrc3=%d ldest=%d fuType=%b fuOpType=%b\n",
     io.out.ctrl.src1Type, io.out.ctrl.src2Type, io.out.ctrl.src3Type, io.out.ctrl.lsrc1, io.out.ctrl.lsrc2, io.out.ctrl.lsrc3, io.out.ctrl.ldest, io.out.ctrl.fuType, io.out.ctrl.fuOpType)
   XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d isRVF=%d imm=%x\n",
-    io.out.ctrl.rfWen, io.out.ctrl.fpWen, io.out.ctrl.isXSTrap, io.out.ctrl.noSpecExec, io.out.ctrl.isBlocked, io.out.ctrl.flushPipe, io.out.ctrl.isRVF, io.out.ctrl.imm)
+    io.out.ctrl.rfWen, io.out.ctrl.fpWen, io.out.ctrl.isXSTrap, io.out.ctrl.noSpecExec, io.out.ctrl.blockBackward, io.out.ctrl.flushPipe, io.out.ctrl.isRVF, io.out.ctrl.imm)
 }

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -203,7 +203,7 @@ object Exu {
   val fmacExeUnitCfg = ExuConfig("FmacExeUnit", Seq(fmacCfg), Int.MaxValue, 0)
   val fmiscExeUnitCfg = ExuConfig(
     "FmiscExeUnit",
-    Seq(fcmpCfg, fmvCfg, f2iCfg, s2dCfg, d2sCfg, fdivSqrtCfg),
+    Seq(fcmpCfg, fminCfg, fmvCfg, fsgnjCfg, f2iCfg, s2dCfg, d2sCfg, fdivSqrtCfg),
     Int.MaxValue, 1
   )
   val ldExeUnitCfg = ExuConfig("LoadExu", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0)

src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala

@@ -4,8 +4,6 @@ import chisel3._
 import chisel3.util._
 import utils._
 import xiangshan.backend.exu.Exu.fmiscExeUnitCfg
-import xiangshan.backend.fu.FunctionUnit
-import xiangshan.backend.fu.FunctionUnit.fmiscSel
 import xiangshan.backend.fu.fpu.FPUOpType._
 import xiangshan.backend.fu.fpu._
 
@@ -13,8 +11,8 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg) {
 
   val frm = IO(Input(UInt(3.W)))
 
-  val fcmp :: fmv :: f2i :: f32toF64 :: f64toF32 :: fdivSqrt :: Nil = supportedFunctionUnits.map(fu => fu.asInstanceOf[FPUSubModule])
-  val toFpUnits = Seq(f32toF64, f64toF32, fdivSqrt)
+  val fcmp :: fmin :: fmv :: fsgnj :: f2i :: f32toF64 :: f64toF32 :: fdivSqrt :: Nil = supportedFunctionUnits.map(fu => fu.asInstanceOf[FPUSubModule])
+  val toFpUnits = Seq(fmin, fsgnj, f32toF64, f64toF32, fdivSqrt)
   val toIntUnits = Seq(fcmp, fmv, f2i)
 
   assert(fpArb.io.in.length == toFpUnits.size)
@@ -50,7 +48,7 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg) {
   )
   val intOutCtrl = io.toInt.bits.uop.ctrl
   io.toInt.bits.data := Mux(
-    (intOutCtrl.isRVF && intOutCtrl.fuOpType === fmv_i2f) ||
+    (intOutCtrl.isRVF && intOutCtrl.fuOpType === fmv_f2i) ||
       intOutCtrl.fuOpType === f2w ||
       intOutCtrl.fuOpType === f2wu,
     SignExt(intArb.io.out.bits.data(31, 0), XLEN),

src/main/scala/xiangshan/backend/fu/FunctionUnit.scala

@@ -233,13 +233,25 @@ object FunctionUnit extends HasXSParameter {
 
   val fcmpCfg = FuConfig(
     fuGen = fcmp _,
-    fuSel = fmiscSel(FU_FCMP),
+    fuSel = (x: FunctionUnit) => fmiscSel(FU_FCMP)(x) && x.io.in.bits.uop.ctrl.rfWen,
     FuType.fmisc, 0, 2, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2)
   )
 
+  val fminCfg = FuConfig(
+    fuGen = fcmp _,
+    fuSel = (x: FunctionUnit) => fmiscSel(FU_FCMP)(x) && x.io.in.bits.uop.ctrl.fpWen,
+    FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2)
+  )
+
+  val fsgnjCfg = FuConfig(
+    fuGen = fmv _,
+    fuSel = (x: FunctionUnit) => fmiscSel(FU_FMV)(x) && x.io.in.bits.uop.ctrl.fpWen,
+    FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(1)
+  )
+
   val fmvCfg = FuConfig(
     fuGen = fmv _,
-    fuSel = fmiscSel(FU_FMV),
+    fuSel = (x: FunctionUnit) => fmiscSel(FU_FMV)(x) && x.io.in.bits.uop.ctrl.rfWen,
     FuType.fmisc, 0, 2, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(1)
   )
 

src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala

@@ -65,7 +65,7 @@ class IntToFloatSingleCycle extends FPUSubModule {
   )
   val resD = Cat(aSignReg, expRounded, mantRounded)
 
-  io.in.ready := true.B
+  io.in.ready := io.out.ready
   io.out.valid := io.in.valid
   io.out.bits.uop := io.in.bits.uop
   io.out.bits.data := Mux(aIsZeroReg, 0.U, Mux(isDoubleReg, resD, resS))

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -81,7 +81,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   io.roqDeqPtr := deqPtrExt
 
   // Dispatch
-  val noSpecEnq = io.dp1Req.map(i => i.bits.ctrl.noSpecExec)
+  val noSpecEnq = io.dp1Req.map(i => i.bits.ctrl.blockBackward)
   val hasNoSpec = RegInit(false.B)
   when(isEmpty){ hasNoSpec:= false.B }
   val validDispatch = io.dp1Req.map(_.valid)