dispatch2: DontCare src3 for Fp and Ls

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -85,6 +85,7 @@ class Dispatch2Int extends XSModule {
     val src2Ready = VecInit((0 until 4).map(i => io.regRdy(i * 2 + 1)))
     enq.bits.src1State := src1Ready(readPortIndex(i))
     enq.bits.src2State := src2Ready(readPortIndex(i))
+    enq.bits.src3State := DontCare
 
     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
       p"srcState(${enq.bits.src1State} ${enq.bits.src2State}) " +

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -83,6 +83,7 @@ class Dispatch2Ls extends XSModule {
       enq.bits.src2State := Mux(io.fromDq(indexVec(i)).bits.ctrl.src2Type === SrcType.fp,
         io.fpRegRdy(i - exuParameters.LduCnt), io.intRegRdy(readPort(i) + 1))
     }
+    enq.bits.src3State := DontCare
 
     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
       p"srcState(${enq.bits.src1State} ${enq.bits.src2State}) " +