From e308959199fcffe0cd465268ceaa4d291a4ee37f Mon Sep 17 00:00:00 2001
From: Lingrui98 <goulingrui15@gmail.com>
Date: Thu, 14 Jan 2021 22:29:24 +0800
Subject: [PATCH] util: use the same base datamodule both for sync and async
 version

---
 src/main/scala/utils/DataModuleTemplate.scala | 41 ++++---------------
 1 file changed, 8 insertions(+), 33 deletions(-)

diff --git a/src/main/scala/utils/DataModuleTemplate.scala b/src/main/scala/utils/DataModuleTemplate.scala
index f0fd314c2..0cb548e58 100644
--- a/src/main/scala/utils/DataModuleTemplate.scala
+++ b/src/main/scala/utils/DataModuleTemplate.scala
@@ -3,7 +3,7 @@ package utils
 import chisel3._
 import chisel3.util._
 
-class AsyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, numWrite: Int) extends Module {
+class DataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, numWrite: Int, isSync: Boolean) extends Module {
   val io = IO(new Bundle {
     val raddr = Vec(numRead,  Input(UInt(log2Up(numEntries).W)))
     val rdata = Vec(numRead,  Output(gen))
@@ -12,43 +12,15 @@ class AsyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int,
     val wdata = Vec(numWrite, Input(gen))
   })
 
-  val data = Mem(numEntries, gen)
-
-  // read ports
-  for (i <- 0 until numRead) {
-    io.rdata(i) := data(io.raddr(i))
-  }
-
-  // below is the write ports (with priorities)
-  for (i <- 0 until numWrite) {
-    when (io.wen(i)) {
-      data(io.waddr(i)) := io.wdata(i)
-    }
-  }
-
-  // DataModuleTemplate should not be used when there're any write conflicts
-  for (i <- 0 until numWrite) {
-    for (j <- i+1 until numWrite) {
-      assert(!(io.wen(i) && io.wen(j) && io.waddr(i) === io.waddr(j)))
-    }
-  }
-}
-
-class SyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, numWrite: Int) extends Module {
-  val io = IO(new Bundle {
-    val raddr = Vec(numRead,  Input(UInt(log2Up(numEntries).W)))
-    val rdata = Vec(numRead,  Output(gen))
-    val wen   = Vec(numWrite, Input(Bool()))
-    val waddr = Vec(numWrite, Input(UInt(log2Up(numEntries).W)))
-    val wdata = Vec(numWrite, Input(gen))
-  })
+  val n = if (isSync) "SyncDataModuleTemplate" else "AsyncDataModuleTemplate"
+  this.suggestName(n)
 
   val data = Mem(numEntries, gen)
 
   // read ports
-  val raddr_reg = RegNext(io.raddr)
+  val raddr = if (isSync) (RegNext(io.raddr)) else io.raddr
   for (i <- 0 until numRead) {
-    io.rdata(i) := data(raddr_reg(i))
+    io.rdata(i) := data(raddr(i))
   }
 
   // below is the write ports (with priorities)
@@ -65,3 +37,6 @@ class SyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, n
     }
   }
 }
+
+class SyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, numWrite: Int, isSync: Boolean = true) extends DataModuleTemplate(gen, numEntries, numRead, numWrite, true)
+class AsyncDataModuleTemplate[T <: Data](gen: T, numEntries: Int, numRead: Int, numWrite: Int, isSync: Boolean = true) extends DataModuleTemplate(gen, numEntries, numRead, numWrite, false)
\ No newline at end of file
-- 
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