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d315f499
编写于
7月 06, 2020
作者:
Y
Yinan Xu
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差异文件
Merge branch 'fix-mul-bug' of github.com:RISCVERS/XiangShan into fix-mul-bug
上级
8757f860
d88da144
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
66 addition
and
32 deletion
+66
-32
src/main/scala/xiangshan/backend/exu/Mul.scala
src/main/scala/xiangshan/backend/exu/Mul.scala
+0
-6
src/test/scala/xiangshan/backend/exu/MduTest.scala
src/test/scala/xiangshan/backend/exu/MduTest.scala
+46
-26
src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
+20
-0
未找到文件。
src/main/scala/xiangshan/backend/exu/Mul.scala
浏览文件 @
d315f499
...
@@ -2,7 +2,6 @@ package xiangshan.backend.exu
...
@@ -2,7 +2,6 @@ package xiangshan.backend.exu
import
chisel3._
import
chisel3._
import
chisel3.util._
import
chisel3.util._
import
chisel3.util.experimental.BoringUtils
import
xiangshan._
import
xiangshan._
import
utils.
{
LookupTree
,
SignExt
,
ZeroExt
,
_
}
import
utils.
{
LookupTree
,
SignExt
,
ZeroExt
,
_
}
import
xiangshan.backend.
{
MDUOpType
,
MULOpType
}
import
xiangshan.backend.
{
MDUOpType
,
MULOpType
}
...
@@ -15,11 +14,6 @@ class Mul extends Exu(FuType.mul.litValue()){
...
@@ -15,11 +14,6 @@ class Mul extends Exu(FuType.mul.litValue()){
val
mul
=
Module
(
new
ArrayMultiplier
(
XLEN
+
1
))
val
mul
=
Module
(
new
ArrayMultiplier
(
XLEN
+
1
))
val
disp_begin
=
WireInit
(
0.
S
(
64.
W
).
asUInt
())
val
disp_end
=
WireInit
(
1111.
S
(
64.
W
).
asUInt
())
BoringUtils
.
addSource
(
disp_begin
,
"DISPLAY_LOG_START"
)
BoringUtils
.
addSource
(
disp_end
,
"DISPLAY_LOG_END"
)
val
signext
=
SignExt
(
_:
UInt
,
XLEN
+
1
)
val
signext
=
SignExt
(
_:
UInt
,
XLEN
+
1
)
val
zeroext
=
ZeroExt
(
_:
UInt
,
XLEN
+
1
)
val
zeroext
=
ZeroExt
(
_:
UInt
,
XLEN
+
1
)
val
mulInputFuncTable
=
List
(
val
mulInputFuncTable
=
List
(
...
...
src/test/scala/xiangshan/backend/exu/MduTest.scala
浏览文件 @
d315f499
...
@@ -4,6 +4,7 @@ import org.scalatest._
...
@@ -4,6 +4,7 @@ import org.scalatest._
import
chiseltest._
import
chiseltest._
import
chisel3._
import
chisel3._
import
chisel3.experimental.BundleLiterals._
import
chisel3.experimental.BundleLiterals._
import
chisel3.util.experimental.BoringUtils
import
chiseltest.experimental.TestOptionBuilder._
import
chiseltest.experimental.TestOptionBuilder._
import
chiseltest.internal.VerilatorBackendAnnotation
import
chiseltest.internal.VerilatorBackendAnnotation
import
noop.MDUOpType
import
noop.MDUOpType
...
@@ -11,6 +12,8 @@ import xiangshan._
...
@@ -11,6 +12,8 @@ import xiangshan._
import
xiangshan.testutils._
import
xiangshan.testutils._
import
xiangshan.testutils.TestCaseGenerator._
import
xiangshan.testutils.TestCaseGenerator._
import
scala.util.Random
...
@@ -20,40 +23,57 @@ class MduTest extends FlatSpec
...
@@ -20,40 +23,57 @@ class MduTest extends FlatSpec
with
ParallelTestExecution
with
ParallelTestExecution
with
HasPartialDecoupledDriver
with
HasPartialDecoupledDriver
{
{
it
should
""
in
{
"MUL"
should
"random enq and deq correctly"
in
{
test
(
new
Mul
){
c
=>
test
(
new
Mul
{
val
disp_begin
=
WireInit
(
0.
S
(
64.
W
).
asUInt
())
val
disp_end
=
WireInit
((-
1
).
S
(
64.
W
).
asUInt
())
BoringUtils
.
addSource
(
disp_begin
,
"DISPLAY_LOG_START"
)
BoringUtils
.
addSource
(
disp_end
,
"DISPLAY_LOG_END"
)
}){
c
=>
c
.
io
.
in
.
initSource
().
setSourceClock
(
c
.
clock
)
c
.
io
.
in
.
initSource
().
setSourceClock
(
c
.
clock
)
c
.
io
.
out
.
initSink
().
setSinkClock
(
c
.
clock
)
c
.
io
.
out
.
initSink
().
setSinkClock
(
c
.
clock
)
c
.
io
.
redirect
.
valid
.
poke
(
true
.
B
)
def
TEST_SIZE
=
100
c
.
io
.
redirect
.
bits
.
isException
.
poke
(
true
.
B
)
val
pcSeq
=
(
0
until
TEST_SIZE
).
map
(
_
=>
Random
.
nextInt
(
0x7fffffff
))
c
.
clock
.
step
(
1
)
c
.
io
.
redirect
.
valid
.
poke
(
false
.
B
)
fork
{
fork
{
// 110
c
.
io
.
in
.
enqueuePartialSeq
(
pcSeq
.
map
(
pc
=>
genMul
(
c
.
io
.
in
.
bits
,
pc
)))
c
.
io
.
in
.
enqueuePartial
(
chiselTypeOf
(
c
.
io
.
in
.
bits
).
Lit
(
}.
fork
{
_
.
uop
.
ctrl
.
fuOpType
->
MDUOpType
.
mulw
,
c
.
io
.
out
.
expectDequeuePartialSeq
(
pcSeq
.
map
(
_
.
uop
.
cf
.
pc
->
1.
U
pc
=>
chiselTypeOf
(
c
.
io
.
out
.
bits
).
Lit
(
))
_
.
uop
.
cf
.
pc
->
pc
.
U
// 111
)
c
.
io
.
in
.
enqueuePartial
(
chiselTypeOf
(
c
.
io
.
in
.
bits
).
Lit
(
_
.
uop
.
ctrl
.
fuOpType
->
MDUOpType
.
mulw
,
_
.
uop
.
cf
.
pc
->
2.
U
))
// 112, 113
c
.
clock
.
step
(
2
)
// 114
c
.
io
.
in
.
enqueuePartial
(
chiselTypeOf
(
c
.
io
.
in
.
bits
).
Lit
(
_
.
uop
.
ctrl
.
fuOpType
->
MDUOpType
.
mulw
,
_
.
uop
.
cf
.
pc
->
3.
U
))
))
}.
join
()
}
}
"MDU"
should
"random enq and deq correctly"
in
{
test
(
new
Mdu
{
val
disp_begin
=
WireInit
(
0.
S
(
64.
W
).
asUInt
())
val
disp_end
=
WireInit
((-
1
).
S
(
64.
W
).
asUInt
())
BoringUtils
.
addSource
(
disp_begin
,
"DISPLAY_LOG_START"
)
BoringUtils
.
addSource
(
disp_end
,
"DISPLAY_LOG_END"
)
}){
c
=>
c
.
io
.
in
.
initSource
().
setSourceClock
(
c
.
clock
)
c
.
io
.
out
.
initSink
().
setSinkClock
(
c
.
clock
)
def
TEST_SIZE
=
50
val
pcSeq
=
(
0
until
TEST_SIZE
).
map
(
_
=>
Random
.
nextInt
(
0x7fffffff
))
fork
{
c
.
io
.
in
.
enqueuePartialSeq
(
pcSeq
.
map
(
pc
=>
{
genDiv
(
c
.
io
.
in
.
bits
,
pc
)
}))
}.
fork
{
}.
fork
{
c
.
io
.
out
.
expectDequeuePartial
(
chiselTypeOf
(
c
.
io
.
out
.
bits
).
Lit
())
c
.
io
.
out
.
expectDequeuePartialSeq
(
pcSeq
.
map
(
c
.
io
.
out
.
expectDequeuePartial
(
chiselTypeOf
(
c
.
io
.
out
.
bits
).
Lit
())
pc
=>
chiselTypeOf
(
c
.
io
.
out
.
bits
).
Lit
(
c
.
io
.
out
.
expectDequeuePartial
(
chiselTypeOf
(
c
.
io
.
out
.
bits
).
Lit
())
_
.
uop
.
cf
.
pc
->
pc
.
U
)
))
}.
join
()
}.
join
()
}
}
...
...
src/test/scala/xiangshan/testutils/TestCaseGenerator.scala
浏览文件 @
d315f499
...
@@ -4,12 +4,32 @@ import chisel3._
...
@@ -4,12 +4,32 @@ import chisel3._
import
chisel3.util._
import
chisel3.util._
import
chisel3.experimental.BundleLiterals._
import
chisel3.experimental.BundleLiterals._
import
chiseltest._
import
chiseltest._
import
noop.MDUOpType
import
xiangshan._
import
xiangshan._
import
xiangshan.backend.exu.
{
ALUOpType
,
LSUOpType
}
import
xiangshan.backend.exu.
{
ALUOpType
,
LSUOpType
}
object
TestCaseGenerator
{
object
TestCaseGenerator
{
/*
Generate MUL/DIV Input
*/
def
genMul
(
x
:
=>
ExuInput
,
pc
:
Long
)
:
ExuInput
=
{
chiselTypeOf
(
x
).
Lit
(
_
.
uop
.
ctrl
.
fuOpType
->
MDUOpType
.
mulw
,
_
.
uop
.
cf
.
pc
->
pc
.
U
)
}
def
genDiv
(
x
:
=>
ExuInput
,
pc
:
Long
)
:
ExuInput
=
{
chiselTypeOf
(
x
).
Lit
(
_
.
uop
.
ctrl
.
fuOpType
->
MDUOpType
.
div
,
_
.
uop
.
cf
.
pc
->
pc
.
U
)
}
/*
/*
Generate ALU Input
Generate ALU Input
*/
*/
...
...
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