Merge branch 'add-axu3cg' into 'master'

Add axu3cg

See merge request projectn/noop!16

fpga/board/axu3cg/mk.tcl

+set device xczu3cg-sfvc784-1-e
+
+set script_dir  [file dirname [info script]]
+
+# Add files for system top
+set src_files [list \
+  "[file normalize "${script_dir}/rtl/system_top.v"]" \
+  "[file normalize "${script_dir}/rtl/addr_mapper.v"]" \
+]
+
+# Add files for constraint
+#set xdc_files [list \
+#]
+
+source ${script_dir}/../common.tcl

fpga/board/axu3cg/rtl/addr_mapper.v

+module addr_mapper (
+   `axi_slave_if(s_axi, 64, 8),
+   `axi_master_if(m_axi, 64, 8)
+);
+
+    assign  m_axi_awaddr = {4'd0, 2'b01, s_axi_awaddr[29:0]};
+    assign  m_axi_araddr = {4'd0, 2'b01, s_axi_araddr[29:0]};
+    assign  m_axi_arburst = s_axi_arburst;
+    assign  m_axi_arcache = s_axi_arcache;
+    assign  m_axi_arid    = s_axi_arid   ;
+//    assign  m_axi_aruser  = s_axi_aruser ;
+    assign  m_axi_arlen   = s_axi_arlen  ;
+    assign  m_axi_arlock  = s_axi_arlock ;
+    assign  m_axi_arprot  = s_axi_arprot ;
+    assign  s_axi_arready = m_axi_arready;
+    assign  m_axi_arsize  = s_axi_arsize ;
+    assign  m_axi_arvalid = s_axi_arvalid;
+    assign  m_axi_awburst = s_axi_awburst;
+    assign  m_axi_awcache = s_axi_awcache;
+    assign  m_axi_awid    = s_axi_awid   ;
+//    assign  m_axi_awuser  = s_axi_awuser ;
+    assign  m_axi_awlen   = s_axi_awlen  ;
+    assign  m_axi_awlock  = s_axi_awlock ;
+    assign  m_axi_awprot  = s_axi_awprot ;
+    assign  s_axi_awready = m_axi_awready;
+    assign  m_axi_awsize  = s_axi_awsize ;
+    assign  m_axi_awvalid = s_axi_awvalid;
+    assign  s_axi_bid     = m_axi_bid    ;
+    assign  m_axi_bready  = s_axi_bready ;
+    assign  s_axi_bresp   = m_axi_bresp  ;
+    assign  s_axi_bvalid  = m_axi_bvalid ;
+    assign  s_axi_rdata   = m_axi_rdata  ;
+    assign  s_axi_rid     = m_axi_rid    ;
+    assign  s_axi_rlast   = m_axi_rlast  ;
+    assign  m_axi_rready  = s_axi_rready ;
+    assign  s_axi_rresp   = m_axi_rresp  ;
+    assign  s_axi_rvalid  = m_axi_rvalid ;
+    assign  m_axi_wdata   = s_axi_wdata  ;
+    assign  m_axi_wlast   = s_axi_wlast  ;
+    assign  s_axi_wready  = m_axi_wready ;
+    assign  m_axi_wstrb   = s_axi_wstrb  ;
+    assign  m_axi_wvalid  = s_axi_wvalid ;
+    assign  m_axi_arqos   = s_axi_arqos  ;
+    assign  m_axi_awqos   = s_axi_awqos  ;
+
+endmodule

fpga/board/axu3cg/rtl/system_top.v

+`include "axi.vh"
+
+module system_top (
+  //output [7:0] led
+);
+
+  `axi_wire(AXI_MEM_MAPPED, 64, 8);
+  `axi_wire(AXI_MEM, 64, 8);
+
+  wire coreclk;
+  wire corerstn;
+  wire clk50;
+  wire rstn50;
+  wire uncoreclk;
+  wire uncorerstn;
+
+  wire noop_uart_tx;
+  wire noop_uart_rx;
+
+  zynq_soc zynq_soc_i (
+    `axi_connect_if(AXI_MEM, AXI_MEM_MAPPED),
+
+    // invert connection
+    .uart_txd(noop_uart_rx),
+    .uart_rxd(noop_uart_tx),
+
+    .coreclk(coreclk),
+    .corerstn(corerstn),
+    .clk50(clk50),
+    .rstn50(rstn50),
+    .uncoreclk(uncoreclk),
+    .uncorerstn(uncorerstn)
+  );
+
+  addr_mapper addr_mapper_i(
+    `axi_connect_if(s_axi, AXI_MEM),
+    `axi_connect_if(m_axi, AXI_MEM_MAPPED)
+  );
+
+  reg corerstn_ff;
+  always@(posedge uncoreclk) begin
+    corerstn_ff <= corerstn;
+  end
+
+  reg corerstn_sync[1:0];
+  always@(posedge coreclk) begin
+    corerstn_sync[0] <= corerstn_ff;
+    corerstn_sync[1] <= corerstn_sync[0];
+  end
+
+  noop noop_i(
+    `axi_connect_if(AXI_MEM, AXI_MEM),
+
+    .uart_txd(noop_uart_tx),
+    .uart_rxd(noop_uart_rx),
+
+    //.VGA_b(VGA_b),
+    //.VGA_r(VGA_r),
+    //.VGA_g(VGA_g),
+    //.VGA_hsync(VGA_hsync),
+    //.VGA_vsync(VGA_vsync),
+
+    .coreclk(coreclk),
+    .corerstn(corerstn_sync[1]),
+    .clk50(clk50),
+    .rstn50(rstn50),
+    .uncoreclk(uncoreclk),
+    .uncorerstn(uncorerstn)
+  );
+
+
+endmodule

fpga/board/common.tcl

@@ -27,7 +27,9 @@ set data_dir    ${script_dir}/data
 set ip_dir      ${script_dir}/ip
 
 create_project $project_name -force -dir $project_dir/ -part ${device}
-set_property board_part $board [current_project]
+if {[info exists board]} {
+  set_property board_part $board [current_project]
+}
 
 # lib files
 set inc_files [list \
@@ -40,7 +42,9 @@ set_property is_global_include true [get_files $inc_files]
 lappend src_files "[file normalize "${fpga_dir}/../build/TopMain.v"]"
 
 add_files -norecurse -fileset sources_1 $src_files
-add_files -norecurse -fileset constrs_1 $xdc_files
+if {[info exists xdc_files]} {
+  add_files -norecurse -fileset constrs_1 $xdc_files
+}
 
 # Block Designs
 add_bd ${fpga_dir}/noop.tcl

fpga/boot/bug-list.md

@@ -2,9 +2,26 @@
 ## sidewinder
 
 To make the SD card work, do the followings
-* `fsbl/psu_init.c`: search for `IOU_SLCR_BANK1_CTRL5_OFFSET`, change `0x2000FFFU` to `0x3FFFFFFU`
+* use a class10 SD card
+* `fsbl/psu_init.c`: search for `IOU_SLCR_BANK1_CTRL5_OFFSET`, change `0x2000FFFU` to `0x3FFFFFFU` (already done inside `mk.tcl`)
+* add "disable-wp;" property to the node of "sdhci@ff170000" in device tree
+
+* remove gem3.phy node
+
+## ultraZ
+
+To make the SD card work, do the followings
 * should use 2016.4 dts
 * add "no-1-8-v;" property to the node of "sdhci@ff170000" in device tree
+* modify gem3.phyc.reg to <0x5>
+
+## axu3cg
+
+* should use u-boot.elf from petalinux
+  * it seems that the default zcu102 config in u-boot can not adapt to this board
+* modify gem3.phyc.reg to <0x1>
+* remove `pinctrl-names` and `pinctrl-0` property from node `uart1`
+  * this will fix the issue of unable to input in linux
 
 ## u-boot
 

fpga/boot/mk.tcl

@@ -25,7 +25,7 @@ switch -regexp -- $brd {
     set brd_version zedboard
     set arch zynq
   }
-  zcu102|sidewinder|ultraZ {
+  zcu102|sidewinder|ultraZ|axu3cg {
     set processor psu_cortexa53_0
     set brd_version zcu102-rev1.0
     set arch zynqmp