diff --git a/fpga/board/axu3cg/bd/prm.tcl b/fpga/board/axu3cg/bd/prm.tcl new file mode 100644 index 0000000000000000000000000000000000000000..37b2e49edb41ac153e5e9371a1f073c1c98076ad --- /dev/null +++ b/fpga/board/axu3cg/bd/prm.tcl @@ -0,0 +1,2299 @@ + +################################################################ +# This is a generated script based on design: zynq_soc +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2019.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source zynq_soc_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xczu3cg-sfvc784-1-e +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name zynq_soc + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_protocol_converter:2.1\ +xilinx.com:ip:axi_crossbar:2.1\ +xilinx.com:ip:axi_uartlite:2.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:zynq_ultra_ps_e:3.3\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: hier_clkrst +proc create_hier_cell_hier_clkrst { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_hier_clkrst() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI + + + # Create pins + create_bd_pin -dir O -type clk clk50 + create_bd_pin -dir I -type clk clk_in1 + create_bd_pin -dir O -type clk coreclk + create_bd_pin -dir O -from 0 -to 0 corerstn + create_bd_pin -dir O -from 0 -to 0 -type rst interconnect_aresetn + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir O -from 0 -to 0 -type rst rstn50 + create_bd_pin -dir O -type clk uncoreclk + create_bd_pin -dir O -from 0 -to 0 -type rst uncorerstn + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_ALL_OUTPUTS {1} \ + CONFIG.C_GPIO_WIDTH {1} \ + ] $axi_gpio_0 + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {100.0} \ + CONFIG.CLKOUT1_DRIVES {BUFG} \ + CONFIG.CLKOUT1_JITTER {94.863} \ + CONFIG.CLKOUT1_PHASE_ERROR {87.181} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {300} \ + CONFIG.CLKOUT2_DRIVES {BUFG} \ + CONFIG.CLKOUT2_JITTER {115.833} \ + CONFIG.CLKOUT2_PHASE_ERROR {87.181} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_DRIVES {BUFG} \ + CONFIG.CLKOUT3_JITTER {132.685} \ + CONFIG.CLKOUT3_PHASE_ERROR {87.181} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_DRIVES {Buffer} \ + CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT4_USED {false} \ + CONFIG.CLKOUT5_DRIVES {Buffer} \ + CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLK_OUT1_PORT {coreclk} \ + CONFIG.CLK_OUT2_PORT {uncoreclk} \ + CONFIG.CLK_OUT3_PORT {clk50} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {12.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {10.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.000} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {24} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {1} \ + CONFIG.MMCM_COMPENSATION {AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {3} \ + CONFIG.PHASESHIFT_MODE {WAVEFORM} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ + CONFIG.USE_PHASE_ALIGNMENT {true} \ + ] $clk_wiz_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: uncorerst, and set properties + set uncorerst [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 uncorerst ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI] + + # Create port connections + connect_bd_net -net armv7_processing_system_FCLK_RESET0_N [get_bd_pins resetn] [get_bd_pins clk_wiz_0/resetn] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins uncorerst/ext_reset_in] + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins corerstn] [get_bd_pins axi_gpio_0/gpio_io_o] + connect_bd_net -net clk_wiz_0_clk50 [get_bd_pins clk50] [get_bd_pins clk_wiz_0/clk50] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + connect_bd_net -net clk_wiz_0_coreclk [get_bd_pins coreclk] [get_bd_pins clk_wiz_0/coreclk] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked] [get_bd_pins uncorerst/dcm_locked] + connect_bd_net -net clk_wiz_0_uncoreclk [get_bd_pins uncoreclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins clk_wiz_0/uncoreclk] [get_bd_pins uncorerst/slowest_sync_clk] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins rstn50] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins interconnect_aresetn] [get_bd_pins uncorerst/interconnect_aresetn] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins uncorerstn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins uncorerst/peripheral_aresetn] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins clk_in1] [get_bd_pins clk_wiz_0/clk_in1] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set AXI_MEM [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 AXI_MEM ] + set_property -dict [ list \ + CONFIG.ADDR_WIDTH {32} \ + CONFIG.ARUSER_WIDTH {0} \ + CONFIG.AWUSER_WIDTH {0} \ + CONFIG.BUSER_WIDTH {0} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.HAS_BRESP {1} \ + CONFIG.HAS_BURST {1} \ + CONFIG.HAS_CACHE {1} \ + CONFIG.HAS_LOCK {1} \ + CONFIG.HAS_PROT {1} \ + CONFIG.HAS_QOS {1} \ + CONFIG.HAS_REGION {0} \ + CONFIG.HAS_RRESP {1} \ + CONFIG.HAS_WSTRB {1} \ + CONFIG.ID_WIDTH {5} \ + CONFIG.MAX_BURST_LENGTH {256} \ + CONFIG.NUM_READ_OUTSTANDING {2} \ + CONFIG.NUM_READ_THREADS {1} \ + CONFIG.NUM_WRITE_OUTSTANDING {2} \ + CONFIG.NUM_WRITE_THREADS {1} \ + CONFIG.PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.RUSER_BITS_PER_BYTE {0} \ + CONFIG.RUSER_WIDTH {0} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_BITS_PER_BYTE {0} \ + CONFIG.WUSER_WIDTH {0} \ + ] $AXI_MEM + + set uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 uart ] + + + # Create ports + set clk50 [ create_bd_port -dir O -type clk clk50 ] + set coreclk [ create_bd_port -dir O -type clk coreclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_RESET {pardcore_corerstn} \ + ] $coreclk + set corerstn [ create_bd_port -dir O -from 0 -to 0 corerstn ] + set rstn50 [ create_bd_port -dir O -from 0 -to 0 -type rst rstn50 ] + set uncoreclk [ create_bd_port -dir O -type clk uncoreclk ] + set_property -dict [ list \ + CONFIG.ASSOCIATED_BUSIF {AXI_MEM} \ + ] $uncoreclk + set uncorerstn [ create_bd_port -dir O -from 0 -to 0 -type rst uncorerstn ] + + # Create instance: axi3_to_lite_pc, and set properties + set axi3_to_lite_pc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_converter:2.1 axi3_to_lite_pc ] + set_property -dict [ list \ + CONFIG.TRANSLATION_MODE {2} \ + ] $axi3_to_lite_pc + + # Create instance: axi_crossbar_0, and set properties + set axi_crossbar_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_crossbar:2.1 axi_crossbar_0 ] + set_property -dict [ list \ + CONFIG.CONNECTIVITY_MODE {SASD} \ + CONFIG.M00_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M00_READ_ISSUING {1} \ + CONFIG.M00_WRITE_ISSUING {1} \ + CONFIG.M01_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M01_READ_ISSUING {1} \ + CONFIG.M01_WRITE_ISSUING {1} \ + CONFIG.M02_A00_ADDR_WIDTH {0} \ + CONFIG.M02_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M02_READ_ISSUING {1} \ + CONFIG.M02_WRITE_ISSUING {1} \ + CONFIG.M03_A00_ADDR_WIDTH {0} \ + CONFIG.M03_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M03_READ_ISSUING {1} \ + CONFIG.M03_WRITE_ISSUING {1} \ + CONFIG.M04_A00_ADDR_WIDTH {0} \ + CONFIG.M04_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M04_READ_ISSUING {1} \ + CONFIG.M04_WRITE_ISSUING {1} \ + CONFIG.M05_A00_ADDR_WIDTH {0} \ + CONFIG.M05_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M05_READ_ISSUING {1} \ + CONFIG.M05_WRITE_ISSUING {1} \ + CONFIG.M06_A00_ADDR_WIDTH {0} \ + CONFIG.M06_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M06_READ_ISSUING {1} \ + CONFIG.M06_WRITE_ISSUING {1} \ + CONFIG.M07_A00_ADDR_WIDTH {0} \ + CONFIG.M07_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M07_READ_ISSUING {1} \ + CONFIG.M07_WRITE_ISSUING {1} \ + CONFIG.M08_A00_ADDR_WIDTH {0} \ + CONFIG.M08_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M08_READ_ISSUING {1} \ + CONFIG.M08_WRITE_ISSUING {1} \ + CONFIG.M09_A00_ADDR_WIDTH {0} \ + CONFIG.M09_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M09_READ_ISSUING {1} \ + CONFIG.M09_WRITE_ISSUING {1} \ + CONFIG.M10_A00_ADDR_WIDTH {0} \ + CONFIG.M10_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M10_READ_ISSUING {1} \ + CONFIG.M10_WRITE_ISSUING {1} \ + CONFIG.M11_A00_ADDR_WIDTH {0} \ + CONFIG.M11_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M11_READ_ISSUING {1} \ + CONFIG.M11_WRITE_ISSUING {1} \ + CONFIG.M12_A00_ADDR_WIDTH {0} \ + CONFIG.M12_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M12_READ_ISSUING {1} \ + CONFIG.M12_WRITE_ISSUING {1} \ + CONFIG.M13_A00_ADDR_WIDTH {0} \ + CONFIG.M13_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M13_READ_ISSUING {1} \ + CONFIG.M13_WRITE_ISSUING {1} \ + CONFIG.M14_A00_ADDR_WIDTH {0} \ + CONFIG.M14_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M14_READ_ISSUING {1} \ + CONFIG.M14_WRITE_ISSUING {1} \ + CONFIG.M15_A00_ADDR_WIDTH {0} \ + CONFIG.M15_A00_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A01_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A02_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A03_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A04_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A05_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A06_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A07_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A08_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A09_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A10_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A11_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A12_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A13_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A14_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_A15_BASE_ADDR {0xffffffffffffffff} \ + CONFIG.M15_READ_ISSUING {1} \ + CONFIG.M15_WRITE_ISSUING {1} \ + CONFIG.NUM_MI {2} \ + CONFIG.R_REGISTER {1} \ + CONFIG.S00_READ_ACCEPTANCE {1} \ + CONFIG.S00_SINGLE_THREAD {1} \ + CONFIG.S00_WRITE_ACCEPTANCE {1} \ + CONFIG.S01_READ_ACCEPTANCE {1} \ + CONFIG.S01_WRITE_ACCEPTANCE {1} \ + CONFIG.S02_READ_ACCEPTANCE {1} \ + CONFIG.S02_WRITE_ACCEPTANCE {1} \ + CONFIG.S03_READ_ACCEPTANCE {1} \ + CONFIG.S03_WRITE_ACCEPTANCE {1} \ + CONFIG.S04_READ_ACCEPTANCE {1} \ + CONFIG.S04_WRITE_ACCEPTANCE {1} \ + CONFIG.S05_READ_ACCEPTANCE {1} \ + CONFIG.S05_WRITE_ACCEPTANCE {1} \ + CONFIG.S06_READ_ACCEPTANCE {1} \ + CONFIG.S06_WRITE_ACCEPTANCE {1} \ + CONFIG.S07_READ_ACCEPTANCE {1} \ + CONFIG.S07_WRITE_ACCEPTANCE {1} \ + CONFIG.S08_READ_ACCEPTANCE {1} \ + CONFIG.S08_WRITE_ACCEPTANCE {1} \ + CONFIG.S09_READ_ACCEPTANCE {1} \ + CONFIG.S09_WRITE_ACCEPTANCE {1} \ + CONFIG.S10_READ_ACCEPTANCE {1} \ + CONFIG.S10_WRITE_ACCEPTANCE {1} \ + CONFIG.S11_READ_ACCEPTANCE {1} \ + CONFIG.S11_WRITE_ACCEPTANCE {1} \ + CONFIG.S12_READ_ACCEPTANCE {1} \ + CONFIG.S12_WRITE_ACCEPTANCE {1} \ + CONFIG.S13_READ_ACCEPTANCE {1} \ + CONFIG.S13_WRITE_ACCEPTANCE {1} \ + CONFIG.S14_READ_ACCEPTANCE {1} \ + CONFIG.S14_WRITE_ACCEPTANCE {1} \ + CONFIG.S15_READ_ACCEPTANCE {1} \ + CONFIG.S15_WRITE_ACCEPTANCE {1} \ + ] $axi_crossbar_0 + + # Create instance: axi_uartlite_0, and set properties + set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ + CONFIG.C_BAUDRATE {115200} \ + CONFIG.C_S_AXI_ACLK_FREQ_HZ {99999000} \ + ] $axi_uartlite_0 + + # Create instance: hier_clkrst + create_hier_cell_hier_clkrst [current_bd_instance .] hier_clkrst + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ + CONFIG.NUM_PORTS {1} \ + ] $xlconcat_0 + + # Create instance: zynq_ultra_ps_e_0, and set properties + set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ] + set_property -dict [ list \ + CONFIG.CAN0_BOARD_INTERFACE {custom} \ + CONFIG.CAN1_BOARD_INTERFACE {custom} \ + CONFIG.CSU_BOARD_INTERFACE {custom} \ + CONFIG.DP_BOARD_INTERFACE {custom} \ + CONFIG.GEM0_BOARD_INTERFACE {custom} \ + CONFIG.GEM1_BOARD_INTERFACE {custom} \ + CONFIG.GEM2_BOARD_INTERFACE {custom} \ + CONFIG.GEM3_BOARD_INTERFACE {custom} \ + CONFIG.GPIO_BOARD_INTERFACE {custom} \ + CONFIG.IIC0_BOARD_INTERFACE {custom} \ + CONFIG.IIC1_BOARD_INTERFACE {custom} \ + CONFIG.NAND_BOARD_INTERFACE {custom} \ + CONFIG.PCIE_BOARD_INTERFACE {custom} \ + CONFIG.PJTAG_BOARD_INTERFACE {custom} \ + CONFIG.PMU_BOARD_INTERFACE {custom} \ + CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ + CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ + CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ + CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ + CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \ + CONFIG.PSU_IMPORT_BOARD_PRESET {} \ + CONFIG.PSU_MIO_0_DIRECTION {inout} \ + CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_0_POLARITY {Default} \ + CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_0_SLEW {fast} \ + CONFIG.PSU_MIO_10_DIRECTION {inout} \ + CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_10_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_10_POLARITY {Default} \ + CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_10_SLEW {fast} \ + CONFIG.PSU_MIO_11_DIRECTION {inout} \ + CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_11_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_11_POLARITY {Default} \ + CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_11_SLEW {fast} \ + CONFIG.PSU_MIO_12_DIRECTION {inout} \ + CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_12_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_12_POLARITY {Default} \ + CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_12_SLEW {fast} \ + CONFIG.PSU_MIO_13_DIRECTION {inout} \ + CONFIG.PSU_MIO_13_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_13_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_13_POLARITY {Default} \ + CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_13_SLEW {fast} \ + CONFIG.PSU_MIO_14_DIRECTION {inout} \ + CONFIG.PSU_MIO_14_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_14_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_14_POLARITY {Default} \ + CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_14_SLEW {fast} \ + CONFIG.PSU_MIO_15_DIRECTION {inout} \ + CONFIG.PSU_MIO_15_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_15_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_15_POLARITY {Default} \ + CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_15_SLEW {fast} \ + CONFIG.PSU_MIO_16_DIRECTION {inout} \ + CONFIG.PSU_MIO_16_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_16_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_16_POLARITY {Default} \ + CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_16_SLEW {fast} \ + CONFIG.PSU_MIO_17_DIRECTION {inout} \ + CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_17_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_17_POLARITY {Default} \ + CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_17_SLEW {fast} \ + CONFIG.PSU_MIO_18_DIRECTION {inout} \ + CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_18_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_18_POLARITY {Default} \ + CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_18_SLEW {fast} \ + CONFIG.PSU_MIO_19_DIRECTION {inout} \ + CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_19_POLARITY {Default} \ + CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_19_SLEW {fast} \ + CONFIG.PSU_MIO_1_DIRECTION {inout} \ + CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_1_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_1_POLARITY {Default} \ + CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_1_SLEW {fast} \ + CONFIG.PSU_MIO_20_DIRECTION {inout} \ + CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_20_POLARITY {Default} \ + CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_20_SLEW {fast} \ + CONFIG.PSU_MIO_21_DIRECTION {inout} \ + CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_21_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_21_POLARITY {Default} \ + CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_21_SLEW {fast} \ + CONFIG.PSU_MIO_22_DIRECTION {inout} \ + CONFIG.PSU_MIO_22_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_22_POLARITY {Default} \ + CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_22_SLEW {fast} \ + CONFIG.PSU_MIO_23_DIRECTION {inout} \ + CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_23_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_23_POLARITY {Default} \ + CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_23_SLEW {fast} \ + CONFIG.PSU_MIO_24_DIRECTION {inout} \ + CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_24_POLARITY {Default} \ + CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_24_SLEW {fast} \ + CONFIG.PSU_MIO_25_DIRECTION {inout} \ + CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_25_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_25_POLARITY {Default} \ + CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_25_SLEW {fast} \ + CONFIG.PSU_MIO_26_DIRECTION {inout} \ + CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_26_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_26_POLARITY {Default} \ + CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_26_SLEW {fast} \ + CONFIG.PSU_MIO_27_DIRECTION {out} \ + CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_27_POLARITY {Default} \ + CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_27_SLEW {fast} \ + CONFIG.PSU_MIO_28_DIRECTION {in} \ + CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_28_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_28_POLARITY {Default} \ + CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_28_SLEW {fast} \ + CONFIG.PSU_MIO_29_DIRECTION {out} \ + CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_29_POLARITY {Default} \ + CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_29_SLEW {fast} \ + CONFIG.PSU_MIO_2_DIRECTION {inout} \ + CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_2_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_2_POLARITY {Default} \ + CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_2_SLEW {fast} \ + CONFIG.PSU_MIO_30_DIRECTION {in} \ + CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_30_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_30_POLARITY {Default} \ + CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_30_SLEW {fast} \ + CONFIG.PSU_MIO_31_DIRECTION {inout} \ + CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_31_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_31_POLARITY {Default} \ + CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_31_SLEW {fast} \ + CONFIG.PSU_MIO_32_DIRECTION {inout} \ + CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_32_POLARITY {Default} \ + CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_32_SLEW {fast} \ + CONFIG.PSU_MIO_33_DIRECTION {inout} \ + CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_33_POLARITY {Default} \ + CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_33_SLEW {fast} \ + CONFIG.PSU_MIO_34_DIRECTION {inout} \ + CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_34_POLARITY {Default} \ + CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_34_SLEW {fast} \ + CONFIG.PSU_MIO_35_DIRECTION {inout} \ + CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_35_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_35_POLARITY {Default} \ + CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_35_SLEW {fast} \ + CONFIG.PSU_MIO_36_DIRECTION {out} \ + CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_36_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_36_POLARITY {Default} \ + CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_36_SLEW {fast} \ + CONFIG.PSU_MIO_37_DIRECTION {in} \ + CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_37_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_37_POLARITY {Default} \ + CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_37_SLEW {fast} \ + CONFIG.PSU_MIO_38_DIRECTION {inout} \ + CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_38_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_38_POLARITY {Default} \ + CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_38_SLEW {fast} \ + CONFIG.PSU_MIO_39_DIRECTION {inout} \ + CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_39_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_39_POLARITY {Default} \ + CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_39_SLEW {fast} \ + CONFIG.PSU_MIO_3_DIRECTION {inout} \ + CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_3_POLARITY {Default} \ + CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_3_SLEW {fast} \ + CONFIG.PSU_MIO_40_DIRECTION {inout} \ + CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_40_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_40_POLARITY {Default} \ + CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_40_SLEW {fast} \ + CONFIG.PSU_MIO_41_DIRECTION {inout} \ + CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_41_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_41_POLARITY {Default} \ + CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_41_SLEW {fast} \ + CONFIG.PSU_MIO_42_DIRECTION {inout} \ + CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_42_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_42_POLARITY {Default} \ + CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_42_SLEW {fast} \ + CONFIG.PSU_MIO_43_DIRECTION {inout} \ + CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_43_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_43_POLARITY {Default} \ + CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_43_SLEW {fast} \ + CONFIG.PSU_MIO_44_DIRECTION {in} \ + CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_44_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_44_POLARITY {Default} \ + CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_44_SLEW {fast} \ + CONFIG.PSU_MIO_45_DIRECTION {in} \ + CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_45_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_45_POLARITY {Default} \ + CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_45_SLEW {fast} \ + CONFIG.PSU_MIO_46_DIRECTION {inout} \ + CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_46_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_46_POLARITY {Default} \ + CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_46_SLEW {fast} \ + CONFIG.PSU_MIO_47_DIRECTION {inout} \ + CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_47_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_47_POLARITY {Default} \ + CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_47_SLEW {fast} \ + CONFIG.PSU_MIO_48_DIRECTION {inout} \ + CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_48_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_48_POLARITY {Default} \ + CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_48_SLEW {fast} \ + CONFIG.PSU_MIO_49_DIRECTION {inout} \ + CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_49_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_49_POLARITY {Default} \ + CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_49_SLEW {fast} \ + CONFIG.PSU_MIO_4_DIRECTION {inout} \ + CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_4_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_4_POLARITY {Default} \ + CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_4_SLEW {fast} \ + CONFIG.PSU_MIO_50_DIRECTION {inout} \ + CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_50_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_50_POLARITY {Default} \ + CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_50_SLEW {fast} \ + CONFIG.PSU_MIO_51_DIRECTION {out} \ + CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_51_POLARITY {Default} \ + CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_51_SLEW {fast} \ + CONFIG.PSU_MIO_52_DIRECTION {inout} \ + CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_52_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_52_POLARITY {Default} \ + CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_52_SLEW {fast} \ + CONFIG.PSU_MIO_53_DIRECTION {inout} \ + CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_53_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_53_POLARITY {Default} \ + CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_53_SLEW {fast} \ + CONFIG.PSU_MIO_54_DIRECTION {inout} \ + CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_54_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_54_POLARITY {Default} \ + CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_54_SLEW {fast} \ + CONFIG.PSU_MIO_55_DIRECTION {inout} \ + CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_55_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_55_POLARITY {Default} \ + CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_55_SLEW {fast} \ + CONFIG.PSU_MIO_56_DIRECTION {inout} \ + CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_56_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_56_POLARITY {Default} \ + CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_56_SLEW {fast} \ + CONFIG.PSU_MIO_57_DIRECTION {inout} \ + CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_57_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_57_POLARITY {Default} \ + CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_57_SLEW {fast} \ + CONFIG.PSU_MIO_58_DIRECTION {inout} \ + CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_58_POLARITY {Default} \ + CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_58_SLEW {fast} \ + CONFIG.PSU_MIO_59_DIRECTION {inout} \ + CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_59_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_59_POLARITY {Default} \ + CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_59_SLEW {fast} \ + CONFIG.PSU_MIO_5_DIRECTION {inout} \ + CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_5_POLARITY {Default} \ + CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_5_SLEW {fast} \ + CONFIG.PSU_MIO_60_DIRECTION {inout} \ + CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_60_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_60_POLARITY {Default} \ + CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_60_SLEW {fast} \ + CONFIG.PSU_MIO_61_DIRECTION {inout} \ + CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_61_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_61_POLARITY {Default} \ + CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_61_SLEW {fast} \ + CONFIG.PSU_MIO_62_DIRECTION {inout} \ + CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_62_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_62_POLARITY {Default} \ + CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_62_SLEW {fast} \ + CONFIG.PSU_MIO_63_DIRECTION {inout} \ + CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_63_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_63_POLARITY {Default} \ + CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_63_SLEW {fast} \ + CONFIG.PSU_MIO_64_DIRECTION {out} \ + CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_64_POLARITY {Default} \ + CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_64_SLEW {fast} \ + CONFIG.PSU_MIO_65_DIRECTION {out} \ + CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_65_POLARITY {Default} \ + CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_65_SLEW {fast} \ + CONFIG.PSU_MIO_66_DIRECTION {out} \ + CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_66_POLARITY {Default} \ + CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_66_SLEW {fast} \ + CONFIG.PSU_MIO_67_DIRECTION {out} \ + CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_67_POLARITY {Default} \ + CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_67_SLEW {fast} \ + CONFIG.PSU_MIO_68_DIRECTION {out} \ + CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_68_POLARITY {Default} \ + CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_68_SLEW {fast} \ + CONFIG.PSU_MIO_69_DIRECTION {out} \ + CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_69_POLARITY {Default} \ + CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_69_SLEW {fast} \ + CONFIG.PSU_MIO_6_DIRECTION {inout} \ + CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_6_POLARITY {Default} \ + CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_6_SLEW {fast} \ + CONFIG.PSU_MIO_70_DIRECTION {in} \ + CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_70_POLARITY {Default} \ + CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_70_SLEW {fast} \ + CONFIG.PSU_MIO_71_DIRECTION {in} \ + CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_71_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_71_POLARITY {Default} \ + CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_71_SLEW {fast} \ + CONFIG.PSU_MIO_72_DIRECTION {in} \ + CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_72_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_72_POLARITY {Default} \ + CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_72_SLEW {fast} \ + CONFIG.PSU_MIO_73_DIRECTION {in} \ + CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_73_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_73_POLARITY {Default} \ + CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_73_SLEW {fast} \ + CONFIG.PSU_MIO_74_DIRECTION {in} \ + CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_74_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_74_POLARITY {Default} \ + CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_74_SLEW {fast} \ + CONFIG.PSU_MIO_75_DIRECTION {in} \ + CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_75_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_75_POLARITY {Default} \ + CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_75_SLEW {fast} \ + CONFIG.PSU_MIO_76_DIRECTION {out} \ + CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_76_POLARITY {Default} \ + CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_76_SLEW {fast} \ + CONFIG.PSU_MIO_77_DIRECTION {inout} \ + CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_77_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_77_POLARITY {Default} \ + CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_77_SLEW {fast} \ + CONFIG.PSU_MIO_7_DIRECTION {inout} \ + CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_7_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_7_POLARITY {Default} \ + CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_7_SLEW {fast} \ + CONFIG.PSU_MIO_8_DIRECTION {inout} \ + CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_8_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_8_POLARITY {Default} \ + CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_8_SLEW {fast} \ + CONFIG.PSU_MIO_9_DIRECTION {inout} \ + CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ + CONFIG.PSU_MIO_9_INPUT_TYPE {cmos} \ + CONFIG.PSU_MIO_9_POLARITY {Default} \ + CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ + CONFIG.PSU_MIO_9_SLEW {fast} \ + CONFIG.PSU_MIO_TREE_PERIPHERALS {########################I2C 1#I2C 1#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#I2C 0#I2C 0#UART 1#UART 1#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#############Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3} \ + CONFIG.PSU_MIO_TREE_SIGNALS {########################scl_out#sda_out#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpio1[32]#gpio1[33]#scl_out#sda_out#txd#rxd#gpio1[38]#gpio1[39]#gpio1[40]#gpio1[41]#gpio1[42]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#############rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out} \ + CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ + CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \ + CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ + CONFIG.PSU_SMC_CYCLE_T0 {NA} \ + CONFIG.PSU_SMC_CYCLE_T1 {NA} \ + CONFIG.PSU_SMC_CYCLE_T2 {NA} \ + CONFIG.PSU_SMC_CYCLE_T3 {NA} \ + CONFIG.PSU_SMC_CYCLE_T4 {NA} \ + CONFIG.PSU_SMC_CYCLE_T5 {NA} \ + CONFIG.PSU_SMC_CYCLE_T6 {NA} \ + CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {0} \ + CONFIG.PSU_VALUE_SILVERSION {3} \ + CONFIG.PSU__ACPU0__POWER__ON {1} \ + CONFIG.PSU__ACPU1__POWER__ON {1} \ + CONFIG.PSU__ACPU2__POWER__ON {0} \ + CONFIG.PSU__ACPU3__POWER__ON {0} \ + CONFIG.PSU__ACTUAL__IP {1} \ + CONFIG.PSU__ACT_DDR_FREQ_MHZ {1066.656006} \ + CONFIG.PSU__AFI0_COHERENCY {0} \ + CONFIG.PSU__AFI1_COHERENCY {0} \ + CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ + CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__CAN1__PERIPHERAL__IO {} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__IO {} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {0} \ + CONFIG.PSU__GPU_PP1__POWER__ON {0} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 34 .. 35} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 24 .. 25} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE_HPX_QOS {0} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {0x06} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {0x0} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {0x4} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {0xD021} \ + CONFIG.PSU__PCIE__DEVICE_PORT_TYPE {} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__LINK_SPEED {} \ + CONFIG.PSU__PCIE__MAX_PAYLOAD_SIZE {} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__REF_CLK_FREQ {} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {0x0} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {0x7} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {0x10EE} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {0x10EE} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {FALSE} \ + CONFIG.PSU__PL_CLK2_BUF {FALSE} \ + CONFIG.PSU__PL_CLK3_BUF {FALSE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {0} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {0} \ + CONFIG.PSU__PMU__GPO1__ENABLE {0} \ + CONFIG.PSU__PMU__GPO2__ENABLE {0} \ + CONFIG.PSU__PMU__GPO3__ENABLE {0} \ + CONFIG.PSU__PMU__GPO4__ENABLE {0} \ + CONFIG.PSU__PMU__GPO5__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {0} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;0|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;0|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__IO {} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__IO {} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__IO {} \ + CONFIG.PSU__SATA__REF_CLK_SEL {} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 36 .. 37} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {} \ + CONFIG.PSU__USB0__REF_CLK_SEL {} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__USB__RESET__MODE {} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {1} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {0} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {1} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {0} \ + CONFIG.PSU__USE__S_AXI_GP1 {0} \ + CONFIG.PSU__USE__S_AXI_GP2 {1} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $zynq_ultra_ps_e_0 + + # Create interface connections + connect_bd_intf_net -intf_net AXI_MEM_1 [get_bd_intf_ports AXI_MEM] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD] + connect_bd_intf_net -intf_net axi3_to_lite_pc_M_AXI [get_bd_intf_pins axi3_to_lite_pc/M_AXI] [get_bd_intf_pins axi_crossbar_0/S00_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M00_AXI [get_bd_intf_pins axi_crossbar_0/M00_AXI] [get_bd_intf_pins hier_clkrst/S_AXI] + connect_bd_intf_net -intf_net axi_crossbar_0_M01_AXI [get_bd_intf_pins axi_crossbar_0/M01_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI] + connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports uart] [get_bd_intf_pins axi_uartlite_0/UART] + connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins axi3_to_lite_pc/S_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD] + + # Create port connections + connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports corerstn] [get_bd_pins hier_clkrst/corerstn] + connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net clk_in1_1 [get_bd_pins hier_clkrst/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] + connect_bd_net -net clk_wiz_0_clk50 [get_bd_ports clk50] [get_bd_pins hier_clkrst/clk50] + connect_bd_net -net clk_wiz_0_coreclk [get_bd_ports coreclk] [get_bd_pins hier_clkrst/coreclk] + connect_bd_net -net clk_wiz_0_uncoreclk [get_bd_ports uncoreclk] [get_bd_pins axi3_to_lite_pc/aclk] [get_bd_pins axi_crossbar_0/aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins hier_clkrst/uncoreclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_ports rstn50] [get_bd_pins hier_clkrst/rstn50] + connect_bd_net -net proc_sys_reset_1_interconnect_aresetn [get_bd_pins axi3_to_lite_pc/aresetn] [get_bd_pins axi_crossbar_0/aresetn] [get_bd_pins hier_clkrst/interconnect_aresetn] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_ports uncorerstn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins hier_clkrst/uncorerstn] + connect_bd_net -net resetn_1 [get_bd_pins hier_clkrst/resetn] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0] + connect_bd_net -net xlconcat_0_dout [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0] + + # Create address segments + create_bd_addr_seg -range 0x00001000 -offset 0x80001000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs hier_clkrst/axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0x80000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces AXI_MEM] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] SEG_zynq_ultra_ps_e_0_HP0_DDR_LOW + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/fpga/board/axu3cg/mk.tcl b/fpga/board/axu3cg/mk.tcl new file mode 100644 index 0000000000000000000000000000000000000000..e26ca21de23bb4cb7a5d261f47884bf02a7e120d --- /dev/null +++ b/fpga/board/axu3cg/mk.tcl @@ -0,0 +1,15 @@ +set device xczu3cg-sfvc784-1-e + +set script_dir [file dirname [info script]] + +# Add files for system top +set src_files [list \ + "[file normalize "${script_dir}/rtl/system_top.v"]" \ + "[file normalize "${script_dir}/rtl/addr_mapper.v"]" \ +] + +# Add files for constraint +#set xdc_files [list \ +#] + +source ${script_dir}/../common.tcl diff --git a/fpga/board/axu3cg/rtl/addr_mapper.v b/fpga/board/axu3cg/rtl/addr_mapper.v new file mode 100644 index 0000000000000000000000000000000000000000..10823d4629bacd1e4206e820121054134ee4037f --- /dev/null +++ b/fpga/board/axu3cg/rtl/addr_mapper.v @@ -0,0 +1,46 @@ +module addr_mapper ( + `axi_slave_if(s_axi, 64, 8), + `axi_master_if(m_axi, 64, 8) +); + + assign m_axi_awaddr = {4'd0, 2'b01, s_axi_awaddr[29:0]}; + assign m_axi_araddr = {4'd0, 2'b01, s_axi_araddr[29:0]}; + assign m_axi_arburst = s_axi_arburst; + assign m_axi_arcache = s_axi_arcache; + assign m_axi_arid = s_axi_arid ; +// assign m_axi_aruser = s_axi_aruser ; + assign m_axi_arlen = s_axi_arlen ; + assign m_axi_arlock = s_axi_arlock ; + assign m_axi_arprot = s_axi_arprot ; + assign s_axi_arready = m_axi_arready; + assign m_axi_arsize = s_axi_arsize ; + assign m_axi_arvalid = s_axi_arvalid; + assign m_axi_awburst = s_axi_awburst; + assign m_axi_awcache = s_axi_awcache; + assign m_axi_awid = s_axi_awid ; +// assign m_axi_awuser = s_axi_awuser ; + assign m_axi_awlen = s_axi_awlen ; + assign m_axi_awlock = s_axi_awlock ; + assign m_axi_awprot = s_axi_awprot ; + assign s_axi_awready = m_axi_awready; + assign m_axi_awsize = s_axi_awsize ; + assign m_axi_awvalid = s_axi_awvalid; + assign s_axi_bid = m_axi_bid ; + assign m_axi_bready = s_axi_bready ; + assign s_axi_bresp = m_axi_bresp ; + assign s_axi_bvalid = m_axi_bvalid ; + assign s_axi_rdata = m_axi_rdata ; + assign s_axi_rid = m_axi_rid ; + assign s_axi_rlast = m_axi_rlast ; + assign m_axi_rready = s_axi_rready ; + assign s_axi_rresp = m_axi_rresp ; + assign s_axi_rvalid = m_axi_rvalid ; + assign m_axi_wdata = s_axi_wdata ; + assign m_axi_wlast = s_axi_wlast ; + assign s_axi_wready = m_axi_wready ; + assign m_axi_wstrb = s_axi_wstrb ; + assign m_axi_wvalid = s_axi_wvalid ; + assign m_axi_arqos = s_axi_arqos ; + assign m_axi_awqos = s_axi_awqos ; + +endmodule diff --git a/fpga/board/axu3cg/rtl/system_top.v b/fpga/board/axu3cg/rtl/system_top.v new file mode 100644 index 0000000000000000000000000000000000000000..844fe25a7a8dacf63b3e5be7e7f63a332eca21ac --- /dev/null +++ b/fpga/board/axu3cg/rtl/system_top.v @@ -0,0 +1,72 @@ +`include "axi.vh" + +module system_top ( + //output [7:0] led +); + + `axi_wire(AXI_MEM_MAPPED, 64, 8); + `axi_wire(AXI_MEM, 64, 8); + + wire coreclk; + wire corerstn; + wire clk50; + wire rstn50; + wire uncoreclk; + wire uncorerstn; + + wire noop_uart_tx; + wire noop_uart_rx; + + zynq_soc zynq_soc_i ( + `axi_connect_if(AXI_MEM, AXI_MEM_MAPPED), + + // invert connection + .uart_txd(noop_uart_rx), + .uart_rxd(noop_uart_tx), + + .coreclk(coreclk), + .corerstn(corerstn), + .clk50(clk50), + .rstn50(rstn50), + .uncoreclk(uncoreclk), + .uncorerstn(uncorerstn) + ); + + addr_mapper addr_mapper_i( + `axi_connect_if(s_axi, AXI_MEM), + `axi_connect_if(m_axi, AXI_MEM_MAPPED) + ); + + reg corerstn_ff; + always@(posedge uncoreclk) begin + corerstn_ff <= corerstn; + end + + reg corerstn_sync[1:0]; + always@(posedge coreclk) begin + corerstn_sync[0] <= corerstn_ff; + corerstn_sync[1] <= corerstn_sync[0]; + end + + noop noop_i( + `axi_connect_if(AXI_MEM, AXI_MEM), + + .uart_txd(noop_uart_tx), + .uart_rxd(noop_uart_rx), + + //.VGA_b(VGA_b), + //.VGA_r(VGA_r), + //.VGA_g(VGA_g), + //.VGA_hsync(VGA_hsync), + //.VGA_vsync(VGA_vsync), + + .coreclk(coreclk), + .corerstn(corerstn_sync[1]), + .clk50(clk50), + .rstn50(rstn50), + .uncoreclk(uncoreclk), + .uncorerstn(uncorerstn) + ); + + +endmodule diff --git a/fpga/board/common.tcl b/fpga/board/common.tcl index ca655988aeb8811c2d88bc276b5b76617da53207..c5f157e0b683bfb69e5f180bab51e99632e50bd2 100644 --- a/fpga/board/common.tcl +++ b/fpga/board/common.tcl @@ -27,7 +27,9 @@ set data_dir ${script_dir}/data set ip_dir ${script_dir}/ip create_project $project_name -force -dir $project_dir/ -part ${device} -set_property board_part $board [current_project] +if {[info exists board]} { + set_property board_part $board [current_project] +} # lib files set inc_files [list \ @@ -40,7 +42,9 @@ set_property is_global_include true [get_files $inc_files] lappend src_files "[file normalize "${fpga_dir}/../build/TopMain.v"]" add_files -norecurse -fileset sources_1 $src_files -add_files -norecurse -fileset constrs_1 $xdc_files +if {[info exists xdc_files]} { + add_files -norecurse -fileset constrs_1 $xdc_files +} # Block Designs add_bd ${fpga_dir}/noop.tcl diff --git a/fpga/boot/axu3cg/u-boot.elf b/fpga/boot/axu3cg/u-boot.elf new file mode 100755 index 0000000000000000000000000000000000000000..72363aa504ad4488f8ef45fd1f932f2c0c6e8673 Binary files /dev/null and b/fpga/boot/axu3cg/u-boot.elf differ diff --git a/fpga/boot/bug-list.md b/fpga/boot/bug-list.md index 151e86bb612ac4a9ffb0809435d2e4f332877db8..2e75b592521346519dc36e9869355e45ac844eab 100644 --- a/fpga/boot/bug-list.md +++ b/fpga/boot/bug-list.md @@ -2,9 +2,26 @@ ## sidewinder To make the SD card work, do the followings -* `fsbl/psu_init.c`: search for `IOU_SLCR_BANK1_CTRL5_OFFSET`, change `0x2000FFFU` to `0x3FFFFFFU` +* use a class10 SD card +* `fsbl/psu_init.c`: search for `IOU_SLCR_BANK1_CTRL5_OFFSET`, change `0x2000FFFU` to `0x3FFFFFFU` (already done inside `mk.tcl`) +* add "disable-wp;" property to the node of "sdhci@ff170000" in device tree + +* remove gem3.phy node + +## ultraZ + +To make the SD card work, do the followings * should use 2016.4 dts * add "no-1-8-v;" property to the node of "sdhci@ff170000" in device tree +* modify gem3.phyc.reg to <0x5> + +## axu3cg + +* should use u-boot.elf from petalinux + * it seems that the default zcu102 config in u-boot can not adapt to this board +* modify gem3.phyc.reg to <0x1> +* remove `pinctrl-names` and `pinctrl-0` property from node `uart1` + * this will fix the issue of unable to input in linux ## u-boot diff --git a/fpga/boot/mk.tcl b/fpga/boot/mk.tcl index 0866d175c85e4b157e393c5ab68f0102bb5eb78d..8543fee66084250cb4489af0013d2347d4e931eb 100644 --- a/fpga/boot/mk.tcl +++ b/fpga/boot/mk.tcl @@ -25,7 +25,7 @@ switch -regexp -- $brd { set brd_version zedboard set arch zynq } - zcu102|sidewinder|ultraZ { + zcu102|sidewinder|ultraZ|axu3cg { set processor psu_cortexa53_0 set brd_version zcu102-rev1.0 set arch zynqmp