StoreSet: put LFST into dispatch1

* Future work: optimize timing

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -355,6 +355,8 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
   dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist
   dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl
 //  dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData
+  dispatch.io.csrCtrl <> io.csrCtrl
+  dispatch.io.storeIssue <> io.fromLsBlock.stIn
 
 
   fpBusyTable.io.flush := flushReg

src/main/scala/xiangshan/backend/decode/StoreSet.scala

@@ -137,12 +137,16 @@ class DispatchToLFST extends XSBundle  {
   val ssid = UInt(SSIDWidth.W)
 }
 
+class LookupLFST extends XSBundle  {
+  val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // xor hashed decode pc(VaddrBits-1, 1)
+  val ren = Vec(DecodeWidth, Input(Bool())) // ren iff uop.cf.storeSetHit
+  val rdata = Vec(DecodeWidth, Output(Bool()))
+}
+
 // Last Fetched Store Table
 class LFST extends XSModule  {
   val io = IO(new Bundle {
-    val raddr = Vec(DecodeWidth, Input(UInt(MemPredPCWidth.W))) // xor hashed decode pc(VaddrBits-1, 1)
-    val ren = Vec(DecodeWidth, Input(Bool())) // ren iff uop.cf.storeSetHit
-    val rdata = Vec(DecodeWidth, Output(Bool()))
+    val lookup = new LookupLFST
     // val update = Input(new MemPredUpdateReq) // RegNext should be added outside
     // when redirect, mark canceled store as invalid
     val redirect = Input(Valid(new Redirect))
@@ -161,7 +165,8 @@ class LFST extends XSModule  {
 
   // read LFST in rename stage
   for (i <- 0 until DecodeWidth) {
-    io.rdata(i) := (valid(io.raddr(i)) && io.ren(i) || io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
+    io.lookup.rdata(i) := (valid(io.lookup.raddr(i)) && io.lookup.ren(i) || 
+      io.csrCtrl.no_spec_load) && !io.csrCtrl.lvpred_disable
   }
 
   // when store is dispatched, mark it as valid

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -50,6 +50,9 @@ class Dispatch extends XSModule {
       val fpIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W)))
       // ls: hardwired to (0, 1, 2, 4)
     }
+    val csrCtrl = Input(new CustomCSRCtrlIO)
+    // LFST state sync
+    val storeIssue = Vec(StorePipelineWidth, Flipped(Valid(new ExuInput)))
   })
 
   val dispatch1 = Module(new Dispatch1)
@@ -74,6 +77,10 @@ class Dispatch extends XSModule {
   dispatch1.io.toFpDq <> fpDq.io.enq
   dispatch1.io.toLsDq <> lsDq.io.enq
   dispatch1.io.allocPregs <> io.allocPregs
+  dispatch1.io.csrCtrl <> io.csrCtrl
+  dispatch1.io.storeIssue <> io.storeIssue
+  dispatch1.io.redirect <> io.redirect
+  dispatch1.io.flush <> io.flush
 
   // dispatch queue: queue uops and dispatch them to different reservation stations or issue queues
   // it may cancel the uops

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -9,7 +9,7 @@ import xiangshan.backend.roq.{RoqPtr, RoqEnqIO}
 import xiangshan.backend.rename.RenameBypassInfo
 import xiangshan.mem.LsqEnqIO
 import xiangshan.backend.fu.HasExceptionNO
-import xiangshan.backend.decode.DispatchToLFST
+import xiangshan.backend.decode.{LFST, DispatchToLFST, LookupLFST}
 
 
 class PreDispatchInfo extends XSBundle {
@@ -47,9 +47,28 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     }
     // to store set LFST
     val lfst = Vec(RenameWidth, Valid(new DispatchToLFST))
+    // flush or replay, for LFST
+    val redirect = Flipped(ValidIO(new Redirect))
+    val flush = Input(Bool())
+    // LFST ctrl
+    val csrCtrl = Input(new CustomCSRCtrlIO)
+    // LFST state sync
+    val storeIssue = Vec(StorePipelineWidth, Flipped(Valid(new ExuInput)))
   })
 
 
+  /**
+    * Store set LFST lookup
+    */
+  // store set LFST lookup may start from rename for better timing
+
+  val lfst = Module(new LFST)
+  lfst.io.redirect <> io.redirect
+  lfst.io.flush <> io.flush
+  lfst.io.dispatch := io.lfst
+  lfst.io.storeIssue <> io.storeIssue
+  lfst.io.csrCtrl <> io.csrCtrl
+
   /**
     * Part 1: choose the target dispatch queue and the corresponding write ports
     */
@@ -128,6 +147,11 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     updatedUop(i).lqIdx  := io.enqLsq.resp(i).lqIdx
     updatedUop(i).sqIdx  := io.enqLsq.resp(i).sqIdx
 
+    // lookup store set LFST
+    lfst.io.lookup.raddr(i) := updatedUop(i).cf.ssid
+    lfst.io.lookup.ren(i) := updatedUop(i).cf.storeSetHit
+    updatedUop(i).cf.loadWaitBit := lfst.io.lookup.rdata(i)
+
     // update store set LFST
     io.lfst(i).valid := io.fromRename(i).valid && updatedUop(i).cf.storeSetHit && isStore(i)
     // or io.fromRename(i).ready && updatedUop(i).cf.storeSetHit && isStore(i), which is much slower