StoreSet: put SSIT into decode stage

src/main/scala/xiangshan/Bundle.scala

@@ -182,6 +182,7 @@ class CtrlFlow extends XSBundle  {
   val crossPageIPFFix = Bool()
   val storeSetHit = Bool() // inst has been allocated an store set
   val loadWaitBit = Bool() // load inst should not be executed until all former store addr calcuated
+  val ssid = UInt(SSIDWidth.W)
   val ftqPtr = new FtqPtr
   val ftqOffset = UInt(log2Up(PredictWidth).W)
 }
@@ -302,7 +303,6 @@ class MicroOp extends CfCtrl {
   val roqIdx = new RoqPtr
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
-  val ssid = UInt(SSIDWidth.W)
   val diffTestDebugLrScValid = Bool()
   val debugInfo = new PerfDebugInfo
 }

src/main/scala/xiangshan/XSCore.scala

@@ -281,9 +281,9 @@ trait HasXSParameter {
   // load violation predict
   val ResetTimeMax2Pow = 20 //1078576
   val ResetTimeMin2Pow = 10 //1024
-  val MemPredPCWidth = log2Up(WaitTableSize)
   // wait table parameters
   val WaitTableSize = 1024
+  val MemPredPCWidth = log2Up(WaitTableSize)
   // store set parameters
   val SSITSize = WaitTableSize
   val LFSTSize = 32

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -18,7 +18,12 @@ class DecodeStage extends XSModule {
   })
 
   val decoders = Seq.fill(DecodeWidth)(Module(new DecodeUnit))
+
+  // basic wait table load violation predictor (for debug only)
   val waittable = Module(new WaitTable)
+  // store set load violation predictor stage 1: SSIT look up
+  val ssit = Module(new SSIT)
+
   for (i <- 0 until DecodeWidth) {
     decoders(i).io.enq.ctrl_flow <> io.in(i).bits
 
@@ -26,15 +31,21 @@ class DecodeStage extends XSModule {
     waittable.io.raddr(i) := io.in(i).bits.foldpc
     decoders(i).io.enq.ctrl_flow.loadWaitBit := waittable.io.rdata(i)
 
+    // read SSIT, get SSID
+    ssit.io.raddr(i) := io.in(i).bits.foldpc
+    decoders(i).io.enq.ctrl_flow.storeSetHit := ssit.io.rdata(i).valid
+    decoders(i).io.enq.ctrl_flow.ssid := ssit.io.rdata(i).ssid
+
     io.out(i).valid      := io.in(i).valid
     io.out(i).bits       := decoders(i).io.deq.cf_ctrl
     io.in(i).ready       := io.out(i).ready
   }
-
   for (i <- 0 until StorePipelineWidth) {
     waittable.io.update(i) <> RegNext(io.memPredUpdate(i))
   }
   waittable.io.csrCtrl <> io.csrCtrl
+  ssit.io.update <> RegNext(io.memPredUpdate(0))
+  ssit.io.csrCtrl <> io.csrCtrl
 
   val loadWaitBitSet = PopCount(io.out.map(o => o.fire() && o.bits.cf.loadWaitBit))
   XSPerf("loadWaitBitSet", loadWaitBitSet)

src/main/scala/xiangshan/backend/decode/StoreSet.scala

@@ -50,7 +50,7 @@ class SSIT extends XSModule {
 
   // update stage 0
   // RegNext(io.update) while reading SSIT entry for necessary information
-  val MemPredUpdateReqReg = RegEnable(io.update, enable = io.update.valid)
+  val memPredUpdateReqReg = RegEnable(io.update, enable = io.update.valid)
   // load has already been assigned with a store set
   val loadAssigned = RegNext(valid(io.update.ldpc))
   val loadOldSSID = RegNext(ssid(io.update.ldpc))
@@ -63,45 +63,45 @@ class SSIT extends XSModule {
   val winnerSSID = Mux(loadIsWinner, loadOldSSID, storeOldSSID)
 
   // for now we just use lowest bits of ldpc as store set id
-  val ssidAllocate = MemPredUpdateReqReg.ldpc(SSIDWidth-1, 0)
+  val ssidAllocate = memPredUpdateReqReg.ldpc(SSIDWidth-1, 0)
 
   // update stage 1
-  when(MemPredUpdateReqReg.valid){
+  when(memPredUpdateReqReg.valid){
     switch (Cat(loadAssigned, storeAssigned)) {
       // 1. "If neither the load nor the store has been assigned a store set, 
       // one is allocated and assigned to both instructions."
-      is (Cat(false.B, false.B)) {
-        valid(MemPredUpdateReqReg.ldpc) := true.B
-        isload(MemPredUpdateReqReg.ldpc) := true.B
-        ssid(MemPredUpdateReqReg.ldpc) := ssidAllocate
-        valid(MemPredUpdateReqReg.stpc) := true.B
-        isload(MemPredUpdateReqReg.stpc) := false.B
-        ssid(MemPredUpdateReqReg.stpc) := ssidAllocate
+      is ("b00".U(2.W)) {
+        valid(memPredUpdateReqReg.ldpc) := true.B
+        isload(memPredUpdateReqReg.ldpc) := true.B
+        ssid(memPredUpdateReqReg.ldpc) := ssidAllocate
+        valid(memPredUpdateReqReg.stpc) := true.B
+        isload(memPredUpdateReqReg.stpc) := false.B
+        ssid(memPredUpdateReqReg.stpc) := ssidAllocate
       }
       // 2. "If the load has been assigned a store set, but the store has not, 
       // the store is assigned the load’s store set."
-      is (Cat(true.B, false.B)) {
-        valid(MemPredUpdateReqReg.stpc) := true.B
-        isload(MemPredUpdateReqReg.stpc) := false.B
-        ssid(MemPredUpdateReqReg.stpc) := loadOldSSID
+      is ("b10".U(2.W)) {
+        valid(memPredUpdateReqReg.stpc) := true.B
+        isload(memPredUpdateReqReg.stpc) := false.B
+        ssid(memPredUpdateReqReg.stpc) := loadOldSSID
       }
       // 3. "If the store has been assigned a store set, but the load has not, 
       // the load is assigned the store’s store set."
-      is (Cat(false.B, true.B)) {
-        valid(MemPredUpdateReqReg.ldpc) := true.B
-        isload(MemPredUpdateReqReg.ldpc) := true.B
-        ssid(MemPredUpdateReqReg.ldpc) := storeOldSSID
+      is ("b01".U(2.W)) {
+        valid(memPredUpdateReqReg.ldpc) := true.B
+        isload(memPredUpdateReqReg.ldpc) := true.B
+        ssid(memPredUpdateReqReg.ldpc) := storeOldSSID
       }
       // 4. "If both the load and the store have already been assigned store sets, 
       // one of the two store sets is declared the "winner". 
       // The instruction belonging to the loser’s store set is assigned the winner’s store set."
-      is (Cat(true.B, true.B)) {
-        valid(MemPredUpdateReqReg.ldpc) := true.B
-        isload(MemPredUpdateReqReg.ldpc) := true.B
-        ssid(MemPredUpdateReqReg.ldpc) := winnerSSID
-        valid(MemPredUpdateReqReg.stpc) := true.B
-        isload(MemPredUpdateReqReg.stpc) := false.B
-        ssid(MemPredUpdateReqReg.stpc) := winnerSSID
+      is ("b11".U(2.W)) {
+        valid(memPredUpdateReqReg.ldpc) := true.B
+        isload(memPredUpdateReqReg.ldpc) := true.B
+        ssid(memPredUpdateReqReg.ldpc) := winnerSSID
+        valid(memPredUpdateReqReg.stpc) := true.B
+        isload(memPredUpdateReqReg.stpc) := false.B
+        ssid(memPredUpdateReqReg.stpc) := winnerSSID
       }
     }
   }
@@ -116,8 +116,8 @@ class SSIT extends XSModule {
 
   // debug
   for (i <- 0 until StorePipelineWidth) {
-    when (MemPredUpdateReqReg.valid) {
-      XSDebug("%d: SSIT update: load pc %x store pc %x\n", GTimer(), MemPredUpdateReqReg.ldpc, MemPredUpdateReqReg.stpc)
+    when (memPredUpdateReqReg.valid) {
+      XSDebug("%d: SSIT update: load pc %x store pc %x\n", GTimer(), memPredUpdateReqReg.ldpc, memPredUpdateReqReg.stpc)
       XSDebug("%d: SSIT update: load valid %b ssid %x  store valid %b ssid %x\n", GTimer(), loadAssigned, loadOldSSID, storeAssigned,storeOldSSID)
     }
   }
@@ -177,7 +177,7 @@ class LFST extends XSModule  {
   // when store is issued, mark it as invalid
   (0 until exuParameters.StuCnt).map(i => {
     when(io.storeIssue(i).valid){
-      valid(io.storeIssue(i).bits.uop.ssid) := false.B
+      valid(io.storeIssue(i).bits.uop.cf.ssid) := false.B
     }
   })
 

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -133,7 +133,7 @@ class Dispatch1 extends XSModule with HasExceptionNO {
     // or io.fromRename(i).ready && updatedUop(i).cf.storeSetHit && isStore(i), which is much slower
     io.lfst(i).bits.roqIdx := updatedUop(i).roqIdx
     io.lfst(i).bits.sqIdx := updatedUop(i).sqIdx
-    io.lfst(i).bits.ssid := updatedUop(i).ssid
+    io.lfst(i).bits.ssid := updatedUop(i).cf.ssid
   }
 
 

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -129,6 +129,8 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
     io.out(i).bits.crossPageIPFFix := outWire.crossPageIPFFix
     io.out(i).bits.foldpc := outWire.foldpc
     io.out(i).bits.loadWaitBit := DontCare
+    io.out(i).bits.storeSetHit := DontCare
+    io.out(i).bits.ssid := DontCare
   }
   val next_head_vec = VecInit(head_vec.map(_ + numDeq))
   ibuf.io.raddr := VecInit(next_head_vec.map(_.value))