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体验新版 GitCode,发现更多精彩内容 >>
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c694eb8d
编写于
9月 01, 2020
作者:
Z
zhanglinjuan
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
frontend: add log
上级
58e88dcb
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
17 addition
and
12 deletion
+17
-12
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+5
-2
src/main/scala/xiangshan/frontend/IFU.scala
src/main/scala/xiangshan/frontend/IFU.scala
+10
-9
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+2
-1
未找到文件。
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
c694eb8d
...
...
@@ -208,6 +208,8 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
s2_ready
:=
s2_fire
||
!
s2_valid
||
io
.
flush
(
0
)
XSDebug
(
"[Stage 2] v : r : f (%d %d %d) pc: 0x%x mask: %b\n"
,
s2_valid
,
s3_ready
,
s2_fire
,
s2_req_pc
,
s2_req_mask
)
XSDebug
(
p
"[Stage 2] tlb req: v ${io.tlb.req.valid} r ${io.tlb.req.ready} ${io.tlb.req.bits}"
)
XSDebug
(
p
"[Stage 2] tlb resp: v ${io.tlb.resp.valid} r ${io.tlb.resp.ready} ${s2_tlb_resp}"
)
XSDebug
(
"[Stage 2] tag: %x hit:%d\n"
,
s2_tag
,
s2_hit
)
XSDebug
(
"[Stage 2] victimWayMaks:%b invalidVec:%b hitVec:%b waymask:%b\n"
,
victimWayMask
,
invalidVec
.
asUInt
,
hitVec
.
asUInt
,
waymask
.
asUInt
)
...
...
@@ -301,11 +303,12 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
s3_ready
:=
((
io
.
resp
.
fire
()
||
!
s3_valid
)
&&
!
needFlush
)
||
(
needFlush
&&
state
===
s_wait_resp
)
//TODO: coherence
XSDebug
(
"[Stage 3] valid:%d pc: 0x%x mask: %b
\n"
,
s3_valid
,
s3_req_pc
,
s3_req_mask
)
XSDebug
(
"[Stage 3] valid:%d pc: 0x%x mask: %b
ipf:%d\n"
,
s3_valid
,
s3_req_pc
,
s3_req_mask
,
s3_tlb_resp
.
excp
.
pf
.
instr
)
XSDebug
(
"[Stage 3] hit:%d miss:%d waymask:%x \n"
,
s3_hit
,
s3_miss
,
s3_wayMask
.
asUInt
)
XSDebug
(
"[Stage 3] state: %d\n"
,
state
)
XSDebug
(
"[Stage 3] needflush:%d, refilldone:%d"
,
needFlush
,
refill_done
)
XSDebug
(
"[Stage 3] tag: %x idx: %d\n"
,
get_tag
(
s3_req_pc
),
get_idx
(
s3_req_pc
))
XSDebug
(
"[Stage 3] tag: %x idx: %d\n"
,
s3_tag
,
get_idx
(
s3_req_pc
))
XSDebug
(
p
"[Stage 3] tlb resp: ${s3_tlb_resp}"
)
XSDebug
(
"[Chanel A] valid:%d ready:%d\n"
,
bus
.
a
.
valid
,
bus
.
a
.
ready
)
XSDebug
(
"[Chanel D] valid:%d ready:%d data:%x readBeatcnt:%d \n"
,
bus
.
d
.
valid
,
bus
.
d
.
ready
,
bus
.
d
.
bits
.
data
,
readBeatCnt
.
value
)
XSDebug
(
"[Stage 3] ---------Hit Way--------- \n"
)
...
...
src/main/scala/xiangshan/frontend/IFU.scala
浏览文件 @
c694eb8d
...
...
@@ -291,8 +291,8 @@ class IFU extends XSModule with HasIFUConst
XSDebug
(
"[IF1] v=%d fire=%d flush=%d pc=%x ptr=%d mask=%b\n"
,
if1_valid
,
if1_fire
,
if1_flush
,
if1_npc
,
ptr
,
mask
(
if1_npc
))
XSDebug
(
"[IF2] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d snpc=%x\n"
,
if2_valid
,
if2_ready
,
if2_fire
,
if2_redirect
,
if2_flush
,
if2_pc
,
if2_histPtr
,
if2_snpc
)
XSDebug
(
"[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d
\n"
,
if3_valid
,
if3_ready
,
if3_fire
,
if3_redirect
,
if3_flush
,
if3_pc
,
if3_histPtr
)
XSDebug
(
"[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d
\n"
,
if4_valid
,
if4_ready
,
if4_fire
,
if4_redirect
,
if4_flush
,
if4_pc
,
if4_histPtr
)
XSDebug
(
"[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d
crossPageIPF=%d\n"
,
if3_valid
,
if3_ready
,
if3_fire
,
if3_redirect
,
if3_flush
,
if3_pc
,
if3_histPtr
,
crossPageIPF
)
XSDebug
(
"[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d
crossPageIPF=%d\n"
,
if4_valid
,
if4_ready
,
if4_fire
,
if4_redirect
,
if4_flush
,
if4_pc
,
if4_histPtr
,
if4_crossPageIPF
)
XSDebug
(
"[IF1][icacheReq] v=%d r=%d addr=%x\n"
,
io
.
icacheReq
.
valid
,
io
.
icacheReq
.
ready
,
io
.
icacheReq
.
bits
.
addr
)
XSDebug
(
"[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n"
,
headPtr
,
shiftPtr
,
newPtr
,
ptr
)
...
...
@@ -305,18 +305,19 @@ class IFU extends XSModule with HasIFUConst
XSDebug
(
"[IF3][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n"
,
if3_bp
.
redirect
,
if3_bp
.
taken
,
if3_bp
.
jmpIdx
,
if3_bp
.
hasNotTakenBrs
,
if3_bp
.
target
,
if3_bp
.
saveHalfRVI
)
// XSDebug("[IF3][prevHalfInstr] v=%d redirect=%d fetchpc=%x idx=%d tgt=%x taken=%d instr=%x\n\n",
// prev_half_valid, prev_half_redirect, prev_half_fetchpc, prev_half_idx, prev_half_tgt, prev_half_taken, prev_half_instr)
XSDebug
(
"[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n"
,
prevHalfInstr
.
valid
,
prevHalfInstr
.
taken
,
prevHalfInstr
.
fetchpc
,
prevHalfInstr
.
idx
,
prevHalfInstr
.
pc
,
prevHalfInstr
.
target
,
prevHalfInstr
.
instr
)
XSDebug
(
"[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n\n"
,
if3_prevHalfInstr
.
valid
,
if3_prevHalfInstr
.
taken
,
if3_prevHalfInstr
.
fetchpc
,
if3_prevHalfInstr
.
idx
,
if3_prevHalfInstr
.
pc
,
if3_prevHalfInstr
.
target
,
if3_prevHalfInstr
.
instr
)
XSDebug
(
"[IF3][ prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x
ipf=%d
\n"
,
prevHalfInstr
.
valid
,
prevHalfInstr
.
taken
,
prevHalfInstr
.
fetchpc
,
prevHalfInstr
.
idx
,
prevHalfInstr
.
pc
,
prevHalfInstr
.
target
,
prevHalfInstr
.
instr
,
prevHalfInstr
.
ipf
)
XSDebug
(
"[IF3][if3_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x
ipf=%d
\n\n"
,
if3_prevHalfInstr
.
valid
,
if3_prevHalfInstr
.
taken
,
if3_prevHalfInstr
.
fetchpc
,
if3_prevHalfInstr
.
idx
,
if3_prevHalfInstr
.
pc
,
if3_prevHalfInstr
.
target
,
if3_prevHalfInstr
.
instr
,
if3_prevHalfInstr
.
ipf
)
XSDebug
(
"[IF4][predecode] mask=%b\n"
,
if4_pd
.
mask
)
XSDebug
(
"[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n"
,
if4_bp
.
redirect
,
if4_bp
.
taken
,
if4_bp
.
jmpIdx
,
if4_bp
.
hasNotTakenBrs
,
if4_bp
.
target
,
if4_bp
.
saveHalfRVI
)
XSDebug
(
if4_pd
.
pd
(
if4_bp
.
jmpIdx
).
isJal
&&
if4_bp
.
taken
,
"[IF4] cfi is jal! instr=%x target=%x\n"
,
if4_cfi_jal
,
if4_cfi_jal_tgt
)
XSDebug
(
"[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x\n"
,
if4_prevHalfInstr
.
valid
,
if4_prevHalfInstr
.
taken
,
if4_prevHalfInstr
.
fetchpc
,
if4_prevHalfInstr
.
idx
,
if4_prevHalfInstr
.
pc
,
if4_prevHalfInstr
.
target
,
if4_prevHalfInstr
.
instr
)
XSDebug
(
io
.
fetchPacket
.
fire
(),
"[IF4][fetchPacket] v=%d r=%d mask=%b\n"
,
io
.
fetchPacket
.
valid
,
io
.
fetchPacket
.
ready
,
io
.
fetchPacket
.
bits
.
mask
)
XSDebug
(
"[IF4][if4_prevHalfInstr] v=%d taken=%d fetchpc=%x idx=%d pc=%x tgt=%x instr=%x ipf=%d\n"
,
if4_prevHalfInstr
.
valid
,
if4_prevHalfInstr
.
taken
,
if4_prevHalfInstr
.
fetchpc
,
if4_prevHalfInstr
.
idx
,
if4_prevHalfInstr
.
pc
,
if4_prevHalfInstr
.
target
,
if4_prevHalfInstr
.
instr
,
if4_prevHalfInstr
.
ipf
)
XSDebug
(
io
.
fetchPacket
.
fire
(),
"[IF4][fetchPacket] v=%d r=%d mask=%b ipf=%d crossPageIPF=%d\n"
,
io
.
fetchPacket
.
valid
,
io
.
fetchPacket
.
ready
,
io
.
fetchPacket
.
bits
.
mask
,
io
.
fetchPacket
.
bits
.
ipf
,
io
.
fetchPacket
.
bits
.
crossPageIPFFix
)
for
(
i
<-
0
until
PredictWidth
)
{
XSDebug
(
io
.
fetchPacket
.
fire
(),
"[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n"
,
io
.
fetchPacket
.
bits
.
mask
(
i
),
...
...
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
c694eb8d
...
...
@@ -114,7 +114,8 @@ class Ibuffer extends XSModule {
when
(
deqValid
)
{
XSDebug
(
"Deque:\n"
)
for
(
i
<-
0
until
DecodeWidth
){
XSDebug
(
p
"${Hexadecimal(io.out(i).bits.instr)} PC=${Hexadecimal(io.out(i).bits.pc)} v=${io.out(i).valid} r=${io.out(i).ready}\n"
)
XSDebug
(
p
"${Hexadecimal(io.out(i).bits.instr)} PC=${Hexadecimal(io.out(i).bits.pc)} v=${io.out(i).valid} r=${io.out(i).ready} "
+
p
"excpVec=${Binary(io.out(i).bits.exceptionVec.asUInt)} crossPageIPF=${io.out(i).bits.crossPageIPFFix}\n"
)
}
}
...
...
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