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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
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c30bc36c
编写于
7月 16, 2021
作者:
Z
zoujr
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[WIP]IFU: Fix some NullPointer errors
上级
47863f7e
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
21 addition
and
15 deletion
+21
-15
src/main/scala/xiangshan/decoupled-frontend/IFU.scala
src/main/scala/xiangshan/decoupled-frontend/IFU.scala
+11
-12
src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala
src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala
+10
-3
未找到文件。
src/main/scala/xiangshan/decoupled-frontend/IFU.scala
浏览文件 @
c30bc36c
...
@@ -128,7 +128,13 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -128,7 +128,13 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
val
f1_situation
=
RegEnable
(
next
=
f0_situation
,
enable
=
f0_fire
)
val
f1_situation
=
RegEnable
(
next
=
f0_situation
,
enable
=
f0_fire
)
val
f1_doubleLine
=
RegEnable
(
next
=
f0_doubleLine
,
enable
=
f0_fire
)
val
f1_doubleLine
=
RegEnable
(
next
=
f0_doubleLine
,
enable
=
f0_fire
)
val
f1_vSetIdx
=
RegEnable
(
next
=
f0_vSetIdx
,
enable
=
f0_fire
)
val
f1_vSetIdx
=
RegEnable
(
next
=
f0_vSetIdx
,
enable
=
f0_fire
)
val
f1_fire
=
f1_valid
&&
tlbHit
&&
f2_ready
val
f1_fire
=
f1_valid
&&
tlbHit
&&
f2_ready
val
preDecoder
=
Module
(
new
PreDecode
)
val
(
preDecoderIn
,
preDecoderOut
)
=
(
preDecoder
.
io
.
in
,
preDecoder
.
io
.
out
)
//flush generate and to Ftq
val
flush
=
preDecoderOut
.
misOffset
.
valid
when
(
flush
)
{
f1_valid
:=
false
.
B
}
when
(
flush
)
{
f1_valid
:=
false
.
B
}
.
elsewhen
(
f0_fire
)
{
f1_valid
:=
true
.
B
}
.
elsewhen
(
f0_fire
)
{
f1_valid
:=
true
.
B
}
...
@@ -152,8 +158,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -152,8 +158,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
((
replacers
zip
touch_sets
)
zip
touch_ways
).
map
{
case
((
r
,
s
),
w
)
=>
r
.
access
(
s
,
w
)}
((
replacers
zip
touch_sets
)
zip
touch_ways
).
map
{
case
((
r
,
s
),
w
)
=>
r
.
access
(
s
,
w
)}
f1_ready
:=
f2_ready
||
!
f2_valid
val
f1_hit_data
=
VecInit
(
f1_datas
.
zipWithIndex
.
map
{
case
(
bank
,
i
)
=>
val
f1_hit_data
=
VecInit
(
f1_datas
.
zipWithIndex
.
map
{
case
(
bank
,
i
)
=>
val
bank0_hit_data
=
Mux1H
(
bank0_hit_vec
.
asUInt
,
bank
)
val
bank0_hit_data
=
Mux1H
(
bank0_hit_vec
.
asUInt
,
bank
)
val
bank1_hit_data
=
Mux1H
(
bank1_hit_vec
.
asUInt
,
bank
)
val
bank1_hit_data
=
Mux1H
(
bank1_hit_vec
.
asUInt
,
bank
)
...
@@ -173,6 +177,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -173,6 +177,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
val
f2_doubleLine
=
RegEnable
(
next
=
f1_doubleLine
,
enable
=
f1_fire
)
val
f2_doubleLine
=
RegEnable
(
next
=
f1_doubleLine
,
enable
=
f1_fire
)
val
f2_fire
=
io
.
toIbuffer
.
fire
()
val
f2_fire
=
io
.
toIbuffer
.
fire
()
f1_ready
:=
f2_ready
||
!
f2_valid
when
(
flush
)
{
f2_valid
:=
false
.
B
}
when
(
flush
)
{
f2_valid
:=
false
.
B
}
.
elsewhen
(
f1_fire
)
{
f2_valid
:=
true
.
B
}
.
elsewhen
(
f1_fire
)
{
f2_valid
:=
true
.
B
}
.
elsewhen
(
io
.
toIbuffer
.
fire
())
{
f2_valid
:=
false
.
B
}
.
elsewhen
(
io
.
toIbuffer
.
fire
())
{
f2_valid
:=
false
.
B
}
...
@@ -195,7 +201,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -195,7 +201,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
//instruction
//instruction
val
wait_idle
::
wait_send_req
::
wait_finish
::
Nil
=
Enum
(
3
)
val
wait_idle
::
wait_send_req
::
wait_finish
::
Nil
=
Enum
(
3
)
val
wait_state
=
Vec
(
2
,
RegInit
(
wait_idle
))
val
wait_state
=
Vec
Init
(
Seq
.
fill
(
2
)(
RegInit
(
wait_idle
)
))
toMissQueue
<>
DontCare
toMissQueue
<>
DontCare
fromMissQueue
.
map
{
port
=>
port
.
ready
:=
true
.
B
}
fromMissQueue
.
map
{
port
=>
port
.
ready
:=
true
.
B
}
...
@@ -241,12 +247,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -241,12 +247,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
}
}
val
f2_hit_datas
=
RegEnable
(
next
=
f1_hit_data
,
enable
=
f1_fire
)
val
f2_hit_datas
=
RegEnable
(
next
=
f1_hit_data
,
enable
=
f1_fire
)
val
f2_mq_datas
=
Reg
(
VecInit
(
fromMissQueue
.
map
(
p
=>
p
.
bits
.
data
)))
//TODO: Implement miss queue response
val
f2_mq_datas
=
Reg
Init
(
VecInit
(
fromMissQueue
.
map
(
p
=>
p
.
bits
.
data
)))
//TODO: Implement miss queue response
val
f2_datas
=
Mux
(
f2_hit
,
f2_hit_datas
,
f2_mq_datas
)
val
f2_datas
=
Mux
(
f2_hit
,
f2_hit_datas
,
f2_mq_datas
)
val
preDecoder
=
Module
(
new
PreDecode
)
val
(
preDecoderIn
,
preDecoderOut
)
=
(
preDecoder
.
io
.
in
,
preDecoder
.
io
.
out
)
def
cut
(
cacheline
:
UInt
,
start
:
UInt
)
:
Vec
[
UInt
]
={
def
cut
(
cacheline
:
UInt
,
start
:
UInt
)
:
Vec
[
UInt
]
={
val
result
=
Wire
(
Vec
(
17
,
UInt
(
16.
W
)))
val
result
=
Wire
(
Vec
(
17
,
UInt
(
16.
W
)))
...
@@ -272,9 +274,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
...
@@ -272,9 +274,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
io
.
toIbuffer
.
bits
.
foldpc
:=
preDecoderOut
.
pc
.
map
(
i
=>
XORFold
(
i
(
VAddrBits
-
1
,
1
),
MemPredPCWidth
))
io
.
toIbuffer
.
bits
.
foldpc
:=
preDecoderOut
.
pc
.
map
(
i
=>
XORFold
(
i
(
VAddrBits
-
1
,
1
),
MemPredPCWidth
))
//flush generate and to Ftq
val
flush
=
preDecoderOut
.
misOffset
.
valid
toFtq
.
pdWb
.
valid
:=
(
f2_valid
&&
f2_hit
)
||
miss_all_fix
toFtq
.
pdWb
.
valid
:=
(
f2_valid
&&
f2_hit
)
||
miss_all_fix
toFtq
.
pdWb
.
bits
.
pc
:=
preDecoderOut
.
pc
toFtq
.
pdWb
.
bits
.
pc
:=
preDecoderOut
.
pc
toFtq
.
pdWb
.
bits
.
pd
:=
preDecoderOut
.
pd
toFtq
.
pdWb
.
bits
.
pd
:=
preDecoderOut
.
pd
...
...
src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala
浏览文件 @
c30bc36c
...
@@ -100,7 +100,14 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
...
@@ -100,7 +100,14 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
val
isLastInBlock
=
(
i
==
MAXINSNUM
-
1
).
B
val
isLastInBlock
=
(
i
==
MAXINSNUM
-
1
).
B
val
currentIsRVC
=
isRVC
(
inst
)
&&
HasCExtension
.
B
val
currentIsRVC
=
isRVC
(
inst
)
&&
HasCExtension
.
B
val
lastIsValidEnd
=
validEnd
(
i
-
1
)
||
isFirstInBlock
||
!
HasCExtension
.
B
// TODO: when i == 0
// val lastIsValidEnd = if(i == 0) true.B else validEnd(i-1)) || isFirstInBlock || !HasCExtension.B
val
lastIsValidEnd
=
Wire
(
Bool
())
if
(
i
==
0
)
{
lastIsValidEnd
:=
true
.
B
||
isFirstInBlock
||
!
HasCExtension
.
B
}
else
{
lastIsValidEnd
:=
validEnd
(
i
-
1
)
||
isFirstInBlock
||
!
HasCExtension
.
B
}
validStart
(
i
)
:=
lastIsValidEnd
||
!
HasCExtension
.
B
validStart
(
i
)
:=
lastIsValidEnd
||
!
HasCExtension
.
B
validEnd
(
i
)
:=
validStart
(
i
)
&&
currentIsRVC
||
!
validStart
(
i
)
||
!
HasCExtension
.
B
validEnd
(
i
)
:=
validStart
(
i
)
&&
currentIsRVC
||
!
validStart
(
i
)
||
!
HasCExtension
.
B
...
@@ -116,7 +123,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
...
@@ -116,7 +123,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
//io.out.pd(i).excType := ExcType.notExc
//io.out.pd(i).excType := ExcType.notExc
expander
.
io
.
in
:=
inst
expander
.
io
.
in
:=
inst
io
.
out
.
instrs
(
i
)
:=
expander
.
io
.
out
.
bits
io
.
out
.
instrs
(
i
)
:=
expander
.
io
.
out
.
bits
io
.
out
.
pc
(
i
)
:=
pcStart
+
(
i
<<
1
).
U
(
log2Ceil
(
MAXINSNUM
).
W
)
io
.
out
.
pc
(
i
)
:=
pcStart
+
(
i
<<
1
).
U
(
(
log2Ceil
(
MAXINSNUM
)+
1
).
W
)
targets
(
i
)
:=
io
.
out
.
pc
(
i
)
+
Mux
(
io
.
out
.
pd
(
i
).
isBr
,
SignExt
(
brOffset
,
XLEN
),
SignExt
(
jalOffset
,
XLEN
))
targets
(
i
)
:=
io
.
out
.
pc
(
i
)
+
Mux
(
io
.
out
.
pd
(
i
).
isBr
,
SignExt
(
brOffset
,
XLEN
),
SignExt
(
jalOffset
,
XLEN
))
...
@@ -135,7 +142,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
...
@@ -135,7 +142,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
val
jalOffset
=
PriorityEncoder
(
isJumpOH
)
val
jalOffset
=
PriorityEncoder
(
isJumpOH
)
val
brOffset
=
PriorityEncoder
(
isBrOH
)
val
brOffset
=
PriorityEncoder
(
isBrOH
)
io
.
out
.
valid
:=
validStart
io
.
out
.
valid
:=
validStart
.
asUInt
()
io
.
out
.
misOffset
.
valid
:=
misPred
.
asUInt
().
orR
()
io
.
out
.
misOffset
.
valid
:=
misPred
.
asUInt
().
orR
()
io
.
out
.
misOffset
.
bits
:=
PriorityEncoder
(
misPred
)
io
.
out
.
misOffset
.
bits
:=
PriorityEncoder
(
misPred
)
...
...
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