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体验新版 GitCode,发现更多精彩内容 >>
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b9f88ac8
编写于
1月 30, 2021
作者:
Z
ZhangZifei
浏览文件
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差异文件
Merge branch 'master' into tlb-tran-timing
上级
e1952057
0e257eae
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
9 addition
and
7 deletion
+9
-7
src/main/scala/xiangshan/backend/ftq/Ftq.scala
src/main/scala/xiangshan/backend/ftq/Ftq.scala
+1
-0
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+1
-1
src/main/scala/xiangshan/cache/tlb.scala
src/main/scala/xiangshan/cache/tlb.scala
+5
-5
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+1
-0
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
+1
-1
未找到文件。
src/main/scala/xiangshan/backend/ftq/Ftq.scala
浏览文件 @
b9f88ac8
...
@@ -259,6 +259,7 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
...
@@ -259,6 +259,7 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
ftq_2r_sram
.
io
.
raddr
(
1
)
:=
req
.
ptr
.
value
ftq_2r_sram
.
io
.
raddr
(
1
)
:=
req
.
ptr
.
value
ftq_2r_sram
.
io
.
ren
(
1
)
:=
true
.
B
ftq_2r_sram
.
io
.
ren
(
1
)
:=
true
.
B
req
.
entry
.
rasTop
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
rasEntry
req
.
entry
.
rasTop
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
rasEntry
req
.
entry
.
rasSp
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
rasSp
req
.
entry
.
hist
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
hist
req
.
entry
.
hist
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
hist
req
.
entry
.
predHist
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
predHist
req
.
entry
.
predHist
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
predHist
req
.
entry
.
specCnt
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
specCnt
req
.
entry
.
specCnt
:=
ftq_2r_sram
.
io
.
rdata
(
1
).
specCnt
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
b9f88ac8
...
@@ -454,7 +454,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
...
@@ -454,7 +454,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
val
commit_w
=
VecInit
(
deqPtrVec
.
map
(
ptr
=>
writebacked
(
ptr
.
value
)))
val
commit_w
=
VecInit
(
deqPtrVec
.
map
(
ptr
=>
writebacked
(
ptr
.
value
)))
val
commit_exception
=
exceptionDataRead
.
zip
(
writebackDataRead
.
map
(
_
.
flushPipe
)).
map
{
case
(
e
,
f
)
=>
e
.
asUInt
.
orR
||
f
}
val
commit_exception
=
exceptionDataRead
.
zip
(
writebackDataRead
.
map
(
_
.
flushPipe
)).
map
{
case
(
e
,
f
)
=>
e
.
asUInt
.
orR
||
f
}
val
commit_block
=
VecInit
((
0
until
CommitWidth
).
map
(
i
=>
!
commit_w
(
i
)))
val
commit_block
=
VecInit
((
0
until
CommitWidth
).
map
(
i
=>
!
commit_w
(
i
)))
val
allowOnlyOneCommit
=
VecInit
(
commit_exception
.
drop
(
1
)
).
asUInt
.
orR
||
intrBitSetReg
val
allowOnlyOneCommit
=
VecInit
(
commit_exception
).
asUInt
.
orR
||
intrBitSetReg
// for instructions that may block others, we don't allow them to commit
// for instructions that may block others, we don't allow them to commit
for
(
i
<-
0
until
CommitWidth
)
{
for
(
i
<-
0
until
CommitWidth
)
{
// defaults: state === s_idle and instructions commit
// defaults: state === s_idle and instructions commit
...
...
src/main/scala/xiangshan/cache/tlb.scala
浏览文件 @
b9f88ac8
...
@@ -421,11 +421,11 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
...
@@ -421,11 +421,11 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
}
}
ptw
.
req
.
bits
:=
Compare
(
ptwReqSeq
).
bits
ptw
.
req
.
bits
:=
Compare
(
ptwReqSeq
).
bits
val
tooManyPf
=
PopCount
(
pf
)
>
5.
U
//
val tooManyPf = PopCount(pf) > 5.U
when
(
tooManyPf
)
{
// when too much pf, just clear
//
when (tooManyPf) { // when too much pf, just clear
XSDebug
(
p
"Too many pf just flush all the pf v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n"
)
//
XSDebug(p"Too many pf just flush all the pf v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n")
v
.
zipWithIndex
.
map
{
case
(
a
,
i
)
=>
a
:=
a
&
!
pf
(
i
)
}
//
v.zipWithIndex.map{ case (a, i) => a := a & !pf(i) }
}
//
}
// sfence (flush)
// sfence (flush)
when
(
sfence
.
valid
)
{
when
(
sfence
.
valid
)
{
...
...
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
b9f88ac8
...
@@ -55,6 +55,7 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
...
@@ -55,6 +55,7 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
// Ibuffer define
// Ibuffer define
// val ibuf = Reg(Vec(IBufSize, new IBufEntry))
// val ibuf = Reg(Vec(IBufSize, new IBufEntry))
val
ibuf
=
Module
(
new
SyncDataModuleTemplate
(
new
IBufEntry
,
IBufSize
,
DecodeWidth
,
PredictWidth
))
val
ibuf
=
Module
(
new
SyncDataModuleTemplate
(
new
IBufEntry
,
IBufSize
,
DecodeWidth
,
PredictWidth
))
ibuf
.
io
.
wdata
.
map
(
w
=>
dontTouch
(
w
.
ftqOffset
))
val
head_ptr
=
RegInit
(
IbufPtr
(
false
.
B
,
0.
U
))
val
head_ptr
=
RegInit
(
IbufPtr
(
false
.
B
,
0.
U
))
val
next_head_ptr
=
WireInit
(
head_ptr
)
val
next_head_ptr
=
WireInit
(
head_ptr
)
val
tail_vec
=
RegInit
(
VecInit
((
0
until
PredictWidth
).
map
(
_
.
U
.
asTypeOf
(
new
IbufPtr
))))
val
tail_vec
=
RegInit
(
VecInit
((
0
until
PredictWidth
).
map
(
_
.
U
.
asTypeOf
(
new
IbufPtr
))))
...
...
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
浏览文件 @
b9f88ac8
...
@@ -193,7 +193,7 @@ class LoadUnit_S2 extends XSModule with HasLoadHelper {
...
@@ -193,7 +193,7 @@ class LoadUnit_S2 extends XSModule with HasLoadHelper {
// TODO: ECC check
// TODO: ECC check
io
.
out
.
valid
:=
io
.
in
.
valid
&&
!
s2_tlb_miss
&&
(!
s2_cache_replay
||
s2_mmio
)
io
.
out
.
valid
:=
io
.
in
.
valid
&&
!
s2_tlb_miss
&&
(!
s2_cache_replay
||
s2_mmio
||
s2_exception
)
// Inst will be canceled in store queue / lsq,
// Inst will be canceled in store queue / lsq,
// so we do not need to care about flush in load / store unit's out.valid
// so we do not need to care about flush in load / store unit's out.valid
io
.
out
.
bits
:=
io
.
in
.
bits
io
.
out
.
bits
:=
io
.
in
.
bits
...
...
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