Merge branch 'master' into tlb-tran-timing

src/main/scala/xiangshan/backend/ftq/Ftq.scala

@@ -259,6 +259,7 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
       ftq_2r_sram.io.raddr(1) := req.ptr.value
       ftq_2r_sram.io.ren(1) := true.B
       req.entry.rasTop := ftq_2r_sram.io.rdata(1).rasEntry
+      req.entry.rasSp := ftq_2r_sram.io.rdata(1).rasSp
       req.entry.hist := ftq_2r_sram.io.rdata(1).hist
       req.entry.predHist := ftq_2r_sram.io.rdata(1).predHist
       req.entry.specCnt := ftq_2r_sram.io.rdata(1).specCnt

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -454,7 +454,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   val commit_w = VecInit(deqPtrVec.map(ptr => writebacked(ptr.value)))
   val commit_exception = exceptionDataRead.zip(writebackDataRead.map(_.flushPipe)).map{ case (e, f) => e.asUInt.orR || f }
   val commit_block = VecInit((0 until CommitWidth).map(i => !commit_w(i)))
-  val allowOnlyOneCommit = VecInit(commit_exception.drop(1)).asUInt.orR || intrBitSetReg
+  val allowOnlyOneCommit = VecInit(commit_exception).asUInt.orR || intrBitSetReg
   // for instructions that may block others, we don't allow them to commit
   for (i <- 0 until CommitWidth) {
     // defaults: state === s_idle and instructions commit

src/main/scala/xiangshan/cache/tlb.scala

@@ -421,11 +421,11 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
   }
   ptw.req.bits := Compare(ptwReqSeq).bits
 
-  val tooManyPf = PopCount(pf) > 5.U
-  when (tooManyPf) { // when too much pf, just clear
-    XSDebug(p"Too many pf just flush all the pf v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n")
-    v.zipWithIndex.map{ case (a, i) => a := a & !pf(i) }
-  }
+  // val tooManyPf = PopCount(pf) > 5.U
+  // when (tooManyPf) { // when too much pf, just clear
+  //   XSDebug(p"Too many pf just flush all the pf v:${Hexadecimal(VecInit(v).asUInt)} pf:${Hexadecimal(pf.asUInt)}\n")
+  //   v.zipWithIndex.map{ case (a, i) => a := a & !pf(i) }
+  // }
 
   // sfence (flush)
   when (sfence.valid) {

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -55,6 +55,7 @@ class Ibuffer extends XSModule with HasCircularQueuePtrHelper {
   // Ibuffer define
   // val ibuf = Reg(Vec(IBufSize, new IBufEntry))
   val ibuf = Module(new SyncDataModuleTemplate(new IBufEntry, IBufSize, DecodeWidth, PredictWidth))
+  ibuf.io.wdata.map(w => dontTouch(w.ftqOffset))
   val head_ptr = RegInit(IbufPtr(false.B, 0.U))
   val next_head_ptr = WireInit(head_ptr)
   val tail_vec = RegInit(VecInit((0 until PredictWidth).map(_.U.asTypeOf(new IbufPtr))))

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -193,7 +193,7 @@ class LoadUnit_S2 extends XSModule with HasLoadHelper {
 
   // TODO: ECC check
 
-  io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio)
+  io.out.valid := io.in.valid && !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception)
   // Inst will be canceled in store queue / lsq,
   // so we do not need to care about flush in load / store unit's out.valid
   io.out.bits := io.in.bits