Merge pull request #338 from RISCVERS/fix-brq-enq

brq, lsq: fix enqueue logic

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -141,12 +141,13 @@ class Brq extends XSModule with HasCircularQueuePtrHelper {
   )
 
   // branch insts enq
+  val lastCycleRedirect = RegNext(io.memRedirect.valid || io.roqRedirect.valid)
   val validEntries = distanceBetween(tailPtr, headPtr)
   for(i <- 0 until DecodeWidth){
     val offset = if(i == 0) 0.U else PopCount(io.enqReqs.take(i).map(_.valid))
     val brTag = tailPtr + offset
     val idx = brTag.value
-    io.enqReqs(i).ready := validEntries <= (BrqSize - (i + 1)).U
+    io.enqReqs(i).ready := validEntries <= (BrqSize - (i + 1)).U && !lastCycleRedirect
     io.brTags(i) := brTag
     when (io.enqReqs(i).fire()) {
       brQueue(idx).ptrFlag := brTag.flag

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -262,6 +262,8 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
   // LSQ: send out canAccept when both load queue and store queue are ready
   // Dispatch: send instructions to LSQ only when they are ready
   io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept
+  loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept
+  storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept
   for (i <- 0 until RenameWidth) {
     val isStore = CommitType.lsInstIsStore(io.enq.req(i).bits.ctrl.commitType)
 

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -25,6 +25,7 @@ object LqPtr extends HasXSParameter {
 
 class LqEnqIO extends XSBundle {
   val canAccept = Output(Bool())
+  val sqCanAccept = Input(Bool())
   val needAlloc = Vec(RenameWidth, Input(Bool()))
   val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp)))
   val resp = Vec(RenameWidth, Output(new LqPtr))
@@ -87,7 +88,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
     val offset = if (i == 0) 0.U else PopCount(io.enq.needAlloc.take(i))
     val lqIdx = enqPtrExt(offset)
     val index = lqIdx.value
-    when (io.enq.req(i).valid && io.enq.canAccept && !io.brqRedirect.valid) {
+    when (io.enq.req(i).valid && io.enq.canAccept && io.enq.sqCanAccept && !io.brqRedirect.valid) {
       uop(index) := io.enq.req(i).bits
       allocated(index) := true.B
       datavalid(index) := false.B
@@ -101,7 +102,7 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
   }
 
   // when io.brqRedirect.valid, we don't allow eneuque even though it may fire.
-  when (Cat(firedDispatch).orR && io.enq.canAccept && !io.brqRedirect.valid) {
+  when (Cat(firedDispatch).orR && io.enq.canAccept && io.enq.sqCanAccept && !io.brqRedirect.valid) {
     val enqNumber = PopCount(firedDispatch)
     enqPtrExt := VecInit(enqPtrExt.map(_ + enqNumber))
     XSInfo("dispatched %d insts to lq\n", enqNumber)

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -23,6 +23,7 @@ object SqPtr extends HasXSParameter {
 
 class SqEnqIO extends XSBundle {
   val canAccept = Output(Bool())
+  val lqCanAccept = Input(Bool())
   val needAlloc = Vec(RenameWidth, Input(Bool()))
   val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp)))
   val resp = Vec(RenameWidth, Output(new SqPtr))
@@ -76,7 +77,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     val offset = if (i == 0) 0.U else PopCount(io.enq.needAlloc.take(i))
     val sqIdx = enqPtrExt(offset)
     val index = sqIdx.value
-    when (io.enq.req(i).valid && io.enq.canAccept && !io.brqRedirect.valid) {
+    when (io.enq.req(i).valid && io.enq.canAccept && io.enq.lqCanAccept && !io.brqRedirect.valid) {
       uop(index) := io.enq.req(i).bits
       allocated(index) := true.B
       datavalid(index) := false.B
@@ -87,7 +88,7 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     io.enq.resp(i) := sqIdx
   }
 
-  when (Cat(firedDispatch).orR && io.enq.canAccept && !io.brqRedirect.valid) {
+  when (Cat(firedDispatch).orR && io.enq.canAccept && io.enq.lqCanAccept && !io.brqRedirect.valid) {
     val enqNumber = PopCount(firedDispatch)
     enqPtrExt := VecInit(enqPtrExt.map(_ + enqNumber))
     XSInfo("dispatched %d insts to sq\n", enqNumber)