Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
e332af4e
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
12 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
未验证
提交
e332af4e
编写于
12月 21, 2020
作者:
Y
Yinan Xu
提交者:
GitHub
12月 21, 2020
浏览文件
操作
浏览文件
下载
差异文件
Merge pull request #339 from RISCVERS/opt-roq
roq: wrap commitInfo in RoqDataModule
上级
e5a95a54
9ecac1e8
变更
8
展开全部
隐藏空白更改
内联
并排
Showing
8 changed file
with
210 addition
and
172 deletion
+210
-172
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+18
-17
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
+17
-19
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+0
-4
src/main/scala/xiangshan/backend/rename/Rename.scala
src/main/scala/xiangshan/backend/rename/Rename.scala
+12
-9
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+151
-110
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+3
-4
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+4
-5
src/main/scala/xiangshan/package.scala
src/main/scala/xiangshan/package.scala
+5
-4
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
e332af4e
...
...
@@ -219,22 +219,18 @@ class CfCtrl extends XSBundle {
val
brTag
=
new
BrqPtr
}
// Load / Store Index
//
// while separated lq and sq is used, lsIdx consists of lqIdx, sqIdx and l/s type.
trait
HasLSIdx
{
this:
HasXSParameter
=>
// Separate LSQ
class
LSIdx
extends
XSBundle
{
val
lqIdx
=
new
LqPtr
val
sqIdx
=
new
SqPtr
}
class
LSIdx
extends
XSBundle
with
HasLSIdx
{}
// CfCtrl -> MicroOp at Rename Stage
class
MicroOp
extends
CfCtrl
with
HasLSIdx
{
class
MicroOp
extends
CfCtrl
{
val
psrc1
,
psrc2
,
psrc3
,
pdest
,
old_pdest
=
UInt
(
PhyRegIdxWidth
.
W
)
val
src1State
,
src2State
,
src3State
=
SrcState
()
val
roqIdx
=
new
RoqPtr
val
lqIdx
=
new
LqPtr
val
sqIdx
=
new
SqPtr
val
diffTestDebugLrScValid
=
Bool
()
}
...
...
@@ -296,19 +292,24 @@ class CSRSpecialIO extends XSBundle {
val
interrupt
=
Output
(
Bool
())
}
//class ExuIO extends XSBundle {
// val in = Flipped(DecoupledIO(new ExuInput))
// val redirect = Flipped(ValidIO(new Redirect))
// val out = DecoupledIO(new ExuOutput)
// // for csr
// val csrOnly = new CSRSpecialIO
// val mcommit = Input(UInt(3.W))
//}
class
RoqCommitInfo
extends
XSBundle
{
val
ldest
=
UInt
(
5.
W
)
val
rfWen
=
Bool
()
val
fpWen
=
Bool
()
val
commitType
=
CommitType
()
val
pdest
=
UInt
(
PhyRegIdxWidth
.
W
)
val
old_pdest
=
UInt
(
PhyRegIdxWidth
.
W
)
val
lqIdx
=
new
LqPtr
val
sqIdx
=
new
SqPtr
// these should be optimized for synthesis verilog
val
pc
=
UInt
(
VAddrBits
.
W
)
}
class
RoqCommitIO
extends
XSBundle
{
val
isWalk
=
Output
(
Bool
())
val
valid
=
Vec
(
CommitWidth
,
Output
(
Bool
()))
val
uop
=
Vec
(
CommitWidth
,
Output
(
new
MicroOp
))
val
info
=
Vec
(
CommitWidth
,
Output
(
new
RoqCommitInfo
))
def
hasWalkInstr
=
isWalk
&&
valid
.
asUInt
.
orR
def
hasCommitInstr
=
!
isWalk
&&
valid
.
asUInt
.
orR
...
...
src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala
浏览文件 @
e332af4e
...
...
@@ -41,17 +41,18 @@ class Dispatch1 extends XSModule {
* Part 1: choose the target dispatch queue and the corresponding write ports
*/
// valid bits for different dispatch queues
val
isInt
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isIntExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isFp
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isFpExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isLs
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isMemExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isStore
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isStoreExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isAMO
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
req
.
bits
.
ctrl
.
fuType
===
FuType
.
mou
))
val
isInt
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isIntExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isBranch
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
!
req
.
bits
.
cf
.
brUpdate
.
pd
.
notCFI
))
val
isFp
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isFpExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isLs
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isMemExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isStore
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
FuType
.
isStoreExu
(
req
.
bits
.
ctrl
.
fuType
)))
val
isAMO
=
VecInit
(
io
.
fromRename
.
map
(
req
=>
req
.
bits
.
ctrl
.
fuType
===
FuType
.
mou
))
val
isBlockBackward
=
VecInit
(
io
.
fromRename
.
map
(
_
.
bits
.
ctrl
.
blockBackward
))
val
isNoSpecExec
=
VecInit
(
io
.
fromRename
.
map
(
_
.
bits
.
ctrl
.
noSpecExec
))
/**
* Part 2:
* Update commitType, psrc1, psrc2, psrc3, old_pdest for the uops
* Update commitType, psrc1, psrc2, psrc3, old_pdest
, roqIdx, lqIdx, sqIdx
for the uops
*/
val
updatedUop
=
Wire
(
Vec
(
RenameWidth
,
new
MicroOp
))
val
updatedCommitType
=
Wire
(
Vec
(
RenameWidth
,
CommitType
()))
...
...
@@ -61,7 +62,7 @@ class Dispatch1 extends XSModule {
val
updatedOldPdest
=
Wire
(
Vec
(
RenameWidth
,
UInt
(
PhyRegIdxWidth
.
W
)))
for
(
i
<-
0
until
RenameWidth
)
{
updatedCommitType
(
i
)
:=
Cat
(
isLs
(
i
)
&&
!
isAMO
(
i
),
isStore
(
i
)
|
is
Fp
(
i
))
updatedCommitType
(
i
)
:=
Cat
(
isLs
(
i
)
&&
!
isAMO
(
i
),
isStore
(
i
)
|
is
Branch
(
i
))
updatedPsrc1
(
i
)
:=
io
.
fromRename
.
take
(
i
).
map
(
_
.
bits
.
pdest
)
.
zip
(
if
(
i
==
0
)
Seq
()
else
io
.
renameBypass
.
lsrc1_bypass
(
i
-
1
).
asBools
)
.
foldLeft
(
io
.
fromRename
(
i
).
bits
.
psrc1
)
{
...
...
@@ -91,6 +92,10 @@ class Dispatch1 extends XSModule {
updatedUop
(
i
).
old_pdest
:=
updatedOldPdest
(
i
)
// update commitType
updatedUop
(
i
).
ctrl
.
commitType
:=
updatedCommitType
(
i
)
// update roqIdx, lqIdx, sqIdx
updatedUop
(
i
).
roqIdx
:=
io
.
enqRoq
.
resp
(
i
)
updatedUop
(
i
).
lqIdx
:=
io
.
enqLsq
.
resp
(
i
).
lqIdx
updatedUop
(
i
).
sqIdx
:=
io
.
enqLsq
.
resp
(
i
).
sqIdx
}
...
...
@@ -125,9 +130,7 @@ class Dispatch1 extends XSModule {
// (2) previous instructions are ready
val
thisCanActualOut
=
(
0
until
RenameWidth
).
map
(
i
=>
!
thisIsBlocked
(
i
)
&&
notBlockedByPrevious
(
i
))
// input for ROQ and LSQ
// (1) LSQ needs roqIdx; (2) DPQ needs roqIdx and lsIdx
val
updateUopWithIndex
=
Wire
(
Vec
(
RenameWidth
,
new
MicroOp
))
// input for ROQ, LSQ, Dispatch Queue
for
(
i
<-
0
until
RenameWidth
)
{
io
.
enqRoq
.
needAlloc
(
i
)
:=
io
.
fromRename
(
i
).
valid
io
.
enqRoq
.
req
(
i
).
valid
:=
io
.
fromRename
(
i
).
valid
&&
thisCanActualOut
(
i
)
&&
io
.
enqLsq
.
canAccept
&&
io
.
toIntDq
.
canAccept
&&
io
.
toFpDq
.
canAccept
&&
io
.
toLsDq
.
canAccept
...
...
@@ -142,23 +145,18 @@ class Dispatch1 extends XSModule {
XSDebug
(
io
.
enqLsq
.
req
(
i
).
valid
,
p
"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)} receives lq ${io.enqLsq.resp(i).lqIdx} sq ${io.enqLsq.resp(i).sqIdx}\n"
)
updateUopWithIndex
(
i
)
:=
updatedUop
(
i
)
updateUopWithIndex
(
i
).
roqIdx
:=
io
.
enqRoq
.
resp
(
i
)
updateUopWithIndex
(
i
).
lqIdx
:=
io
.
enqLsq
.
resp
(
i
).
lqIdx
updateUopWithIndex
(
i
).
sqIdx
:=
io
.
enqLsq
.
resp
(
i
).
sqIdx
// send uops to dispatch queues
// Note that if one of their previous instructions cannot enqueue, they should not enter dispatch queue.
// We use notBlockedByPrevious here.
io
.
toIntDq
.
req
(
i
).
bits
:=
update
UopWithIndex
(
i
)
io
.
toIntDq
.
req
(
i
).
bits
:=
update
dUop
(
i
)
io
.
toIntDq
.
req
(
i
).
valid
:=
io
.
fromRename
(
i
).
valid
&&
isInt
(
i
)
&&
thisCanActualOut
(
i
)
&&
io
.
enqLsq
.
canAccept
&&
io
.
enqRoq
.
canAccept
&&
io
.
toFpDq
.
canAccept
&&
io
.
toLsDq
.
canAccept
io
.
toFpDq
.
req
(
i
).
bits
:=
update
UopWithIndex
(
i
)
io
.
toFpDq
.
req
(
i
).
bits
:=
update
dUop
(
i
)
io
.
toFpDq
.
req
(
i
).
valid
:=
io
.
fromRename
(
i
).
valid
&&
isFp
(
i
)
&&
thisCanActualOut
(
i
)
&&
io
.
enqLsq
.
canAccept
&&
io
.
enqRoq
.
canAccept
&&
io
.
toIntDq
.
canAccept
&&
io
.
toLsDq
.
canAccept
io
.
toLsDq
.
req
(
i
).
bits
:=
update
UopWithIndex
(
i
)
io
.
toLsDq
.
req
(
i
).
bits
:=
update
dUop
(
i
)
io
.
toLsDq
.
req
(
i
).
valid
:=
io
.
fromRename
(
i
).
valid
&&
isLs
(
i
)
&&
thisCanActualOut
(
i
)
&&
io
.
enqLsq
.
canAccept
&&
io
.
enqRoq
.
canAccept
&&
io
.
toIntDq
.
canAccept
&&
io
.
toFpDq
.
canAccept
...
...
@@ -177,7 +175,7 @@ class Dispatch1 extends XSModule {
XSInfo
(
io
.
recv
(
i
)
&&
io
.
fromRename
(
i
).
valid
,
p
"pc 0x${Hexadecimal(io.fromRename(i).bits.cf.pc)}, type(${isInt(i)}, ${isFp(i)}, ${isLs(i)}), "
+
p
"roq ${update
UopWithIndex(i).roqIdx}, lq ${updateUopWithIndex(i).lqIdx}, sq ${updateUopWithIndex
(i).sqIdx})\n"
p
"roq ${update
dUop(i).roqIdx}, lq ${updatedUop(i).lqIdx}, sq ${updatedUop
(i).sqIdx})\n"
)
io
.
allocPregs
(
i
).
isInt
:=
io
.
fromRename
(
i
).
valid
&&
io
.
fromRename
(
i
).
bits
.
ctrl
.
rfWen
&&
(
io
.
fromRename
(
i
).
bits
.
ctrl
.
ldest
=/=
0.
U
)
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
e332af4e
...
...
@@ -824,10 +824,6 @@ class CSR extends FunctionUnit with HasCSRConst
"MbpRRight"
->
(
0xb0c
,
"perfCntCondMbpRRight"
),
"MbpRWrong"
->
(
0xb0d
,
"perfCntCondMbpRWrong"
),
"RoqWalk"
->
(
0xb0f
,
"perfCntCondRoqWalk"
),
"RoqWaitInt"
->
(
0xb10
,
"perfCntCondRoqWaitInt"
),
"RoqWaitFp"
->
(
0xb11
,
"perfCntCondRoqWaitFp"
),
"RoqWaitLoad"
->
(
0xb12
,
"perfCntCondRoqWaitLoad"
),
"RoqWaitStore"
->
(
0xb13
,
"perfCntCondRoqWaitStore"
),
"DTlbReqCnt0"
->
(
0xb15
,
"perfCntDtlbReqCnt0"
),
"DTlbReqCnt1"
->
(
0xb16
,
"perfCntDtlbReqCnt1"
),
"DTlbReqCnt2"
->
(
0xb17
,
"perfCntDtlbReqCnt2"
),
...
...
src/main/scala/xiangshan/backend/rename/Rename.scala
浏览文件 @
e332af4e
...
...
@@ -55,10 +55,13 @@ class Rename extends XSModule {
def
needDestReg
[
T
<:
CfCtrl
](
fp
:
Boolean
,
x
:
T
)
:
Bool
=
{
{
if
(
fp
)
x
.
ctrl
.
fpWen
else
x
.
ctrl
.
rfWen
&&
(
x
.
ctrl
.
ldest
=/=
0.
U
)}
}
def
needDestRegCommit
[
T
<:
RoqCommitInfo
](
fp
:
Boolean
,
x
:
T
)
:
Bool
=
{
{
if
(
fp
)
x
.
fpWen
else
x
.
rfWen
&&
(
x
.
ldest
=/=
0.
U
)}
}
fpFreeList
.
walk
.
valid
:=
io
.
roqCommits
.
isWalk
intFreeList
.
walk
.
valid
:=
io
.
roqCommits
.
isWalk
fpFreeList
.
walk
.
bits
:=
PopCount
((
0
until
CommitWidth
).
map
(
i
=>
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
(
true
,
io
.
roqCommits
.
uop
(
i
))))
intFreeList
.
walk
.
bits
:=
PopCount
((
0
until
CommitWidth
).
map
(
i
=>
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
(
false
,
io
.
roqCommits
.
uop
(
i
))))
fpFreeList
.
walk
.
bits
:=
PopCount
((
0
until
CommitWidth
).
map
(
i
=>
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
Commit
(
true
,
io
.
roqCommits
.
info
(
i
))))
intFreeList
.
walk
.
bits
:=
PopCount
((
0
until
CommitWidth
).
map
(
i
=>
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
Commit
(
false
,
io
.
roqCommits
.
info
(
i
))))
// walk has higher priority than allocation and thus we don't use isWalk here
fpFreeList
.
req
.
doAlloc
:=
intFreeList
.
req
.
canAlloc
&&
io
.
out
(
0
).
ready
intFreeList
.
req
.
doAlloc
:=
fpFreeList
.
req
.
canAlloc
&&
io
.
out
(
0
).
ready
...
...
@@ -120,21 +123,21 @@ class Rename extends XSModule {
// speculative inst write
val
specWen
=
freeList
.
req
.
allocReqs
(
i
)
&&
freeList
.
req
.
canAlloc
&&
freeList
.
req
.
doAlloc
&&
!
io
.
roqCommits
.
isWalk
// walk back write
val
commitDestValid
=
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
(
fp
,
io
.
roqCommits
.
uop
(
i
))
val
commitDestValid
=
io
.
roqCommits
.
valid
(
i
)
&&
needDestReg
Commit
(
fp
,
io
.
roqCommits
.
info
(
i
))
val
walkWen
=
commitDestValid
&&
io
.
roqCommits
.
isWalk
rat
.
specWritePorts
(
i
).
wen
:=
specWen
||
walkWen
rat
.
specWritePorts
(
i
).
addr
:=
Mux
(
specWen
,
uops
(
i
).
ctrl
.
ldest
,
io
.
roqCommits
.
uop
(
i
).
ctrl
.
ldest
)
rat
.
specWritePorts
(
i
).
wdata
:=
Mux
(
specWen
,
freeList
.
req
.
pdests
(
i
),
io
.
roqCommits
.
uop
(
i
).
old_pdest
)
rat
.
specWritePorts
(
i
).
addr
:=
Mux
(
specWen
,
uops
(
i
).
ctrl
.
ldest
,
io
.
roqCommits
.
info
(
i
)
.
ldest
)
rat
.
specWritePorts
(
i
).
wdata
:=
Mux
(
specWen
,
freeList
.
req
.
pdests
(
i
),
io
.
roqCommits
.
info
(
i
).
old_pdest
)
XSInfo
(
walkWen
,
{
if
(
fp
)
p
"fp"
else
p
"int "
}
+
p
"walk:
pc:${Hexadecimal(io.roqCommits.uop(i).cf.pc)}
"
+
{
if
(
fp
)
p
"fp"
else
p
"int "
}
+
p
"walk: "
+
p
" ldest:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
)
rat
.
archWritePorts
(
i
).
wen
:=
commitDestValid
&&
!
io
.
roqCommits
.
isWalk
rat
.
archWritePorts
(
i
).
addr
:=
io
.
roqCommits
.
uop
(
i
).
ctrl
.
ldest
rat
.
archWritePorts
(
i
).
wdata
:=
io
.
roqCommits
.
uop
(
i
).
pdest
rat
.
archWritePorts
(
i
).
addr
:=
io
.
roqCommits
.
info
(
i
)
.
ldest
rat
.
archWritePorts
(
i
).
wdata
:=
io
.
roqCommits
.
info
(
i
).
pdest
XSInfo
(
rat
.
archWritePorts
(
i
).
wen
,
{
if
(
fp
)
p
"fp"
else
p
"int "
}
+
p
" rat arch: ldest:${rat.archWritePorts(i).addr}"
+
...
...
@@ -142,7 +145,7 @@ class Rename extends XSModule {
)
freeList
.
deallocReqs
(
i
)
:=
rat
.
archWritePorts
(
i
).
wen
freeList
.
deallocPregs
(
i
)
:=
io
.
roqCommits
.
uop
(
i
).
old_pdest
freeList
.
deallocPregs
(
i
)
:=
io
.
roqCommits
.
info
(
i
).
old_pdest
}
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
e332af4e
此差异已折叠。
点击以展开。
src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
浏览文件 @
e332af4e
...
...
@@ -68,8 +68,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
val
isFull
=
enqPtr
===
deqPtr
&&
!
sameFlag
val
allowIn
=
!
isFull
val
loadCommit
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
.
valid
(
i
)
&&
!
io
.
commits
.
isWalk
&&
io
.
commits
.
uop
(
i
).
ctrl
.
commitType
===
CommitType
.
LOAD
)
val
mcommitIdx
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
.
uop
(
i
).
lqIdx
.
value
)
val
loadCommit
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
.
valid
(
i
)
&&
!
io
.
commits
.
isWalk
&&
io
.
commits
.
info
(
i
)
.
commitType
===
CommitType
.
LOAD
)
val
mcommitIdx
=
(
0
until
CommitWidth
).
map
(
i
=>
io
.
commits
.
info
(
i
).
lqIdx
.
value
)
val
deqMask
=
UIntToMask
(
deqPtr
,
LoadQueueSize
)
val
enqMask
=
UIntToMask
(
enqPtr
,
LoadQueueSize
)
...
...
@@ -496,9 +496,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
* Memory mapped IO / other uncached operations
*
*/
val
commitType
=
io
.
commits
.
uop
(
0
).
ctrl
.
commitType
io
.
uncache
.
req
.
valid
:=
pending
(
deqPtr
)
&&
allocated
(
deqPtr
)
&&
commitType
===
CommitType
.
LOAD
&&
io
.
commits
.
info
(
0
).
commitType
===
CommitType
.
LOAD
&&
io
.
roqDeqPtr
===
uop
(
deqPtr
).
roqIdx
&&
!
io
.
commits
.
isWalk
...
...
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
浏览文件 @
e332af4e
...
...
@@ -194,9 +194,8 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
* (5) ROB commits the instruction: same as normal instructions
*/
//(2) when they reach ROB's head, they can be sent to uncache channel
val
commitType
=
io
.
commits
.
uop
(
0
).
ctrl
.
commitType
io
.
uncache
.
req
.
valid
:=
pending
(
deqPtr
)
&&
allocated
(
deqPtr
)
&&
commitType
===
CommitType
.
STORE
&&
io
.
commits
.
info
(
0
).
commitType
===
CommitType
.
STORE
&&
io
.
roqDeqPtr
===
uop
(
deqPtr
).
roqIdx
&&
!
io
.
commits
.
isWalk
...
...
@@ -256,10 +255,10 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
* (2) They will not be cancelled and can be sent to lower level.
*/
for
(
i
<-
0
until
CommitWidth
)
{
val
storeCommit
=
!
io
.
commits
.
isWalk
&&
io
.
commits
.
valid
(
i
)
&&
io
.
commits
.
uop
(
i
).
ctrl
.
commitType
===
CommitType
.
STORE
val
storeCommit
=
!
io
.
commits
.
isWalk
&&
io
.
commits
.
valid
(
i
)
&&
io
.
commits
.
info
(
i
)
.
commitType
===
CommitType
.
STORE
when
(
storeCommit
)
{
commited
(
io
.
commits
.
uop
(
i
).
sqIdx
.
value
)
:=
true
.
B
XSDebug
(
"store commit %d: idx %d
%x\n"
,
i
.
U
,
io
.
commits
.
uop
(
i
).
sqIdx
.
value
,
io
.
commits
.
uop
(
i
).
cf
.
pc
)
commited
(
io
.
commits
.
info
(
i
).
sqIdx
.
value
)
:=
true
.
B
XSDebug
(
"store commit %d: idx %d
\n"
,
i
.
U
,
io
.
commits
.
info
(
i
).
sqIdx
.
value
)
}
}
...
...
src/main/scala/xiangshan/package.scala
浏览文件 @
e332af4e
...
...
@@ -85,13 +85,14 @@ package object xiangshan {
}
object
CommitType
{
def
INT
=
"b00"
.
U
// int
def
FP
=
"b01"
.
U
// fp
def
LOAD
=
"b10"
.
U
// load
def
STORE
=
"b11"
.
U
// store
def
NORMAL
=
"b00"
.
U
// int/fp
def
BRANCH
=
"b01"
.
U
// branch
def
LOAD
=
"b10"
.
U
// load
def
STORE
=
"b11"
.
U
// store
def
apply
()
=
UInt
(
2.
W
)
def
isLoadStore
(
commitType
:
UInt
)
=
commitType
(
1
)
def
lsInstIsStore
(
commitType
:
UInt
)
=
commitType
(
0
)
def
isBranch
(
commitType
:
UInt
)
=
commitType
(
0
)
&&
!
commitType
(
1
)
}
}
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录