diff --git a/src/main/scala/utils/LogUtils.scala b/src/main/scala/utils/LogUtils.scala
index 0ba2a87c626c02a5960cf2d04ad4febdc2f7e33b..b97bc84920222fb6a4e836eed912ec36173dd83e 100644
--- a/src/main/scala/utils/LogUtils.scala
+++ b/src/main/scala/utils/LogUtils.scala
@@ -120,6 +120,13 @@ object XSPerf extends HasXSParameter {
       if (!env.FPGAPlatform && !env.DualCore) {
         ExcitingUtils.addSink(xstrap, "XSTRAP", ConnectionType.Debug)
       }
+      val perfClean = WireInit(false.B)
+      val perfDump = WireInit(false.B)
+      ExcitingUtils.addSink(perfClean, "XSPERF_CLEAN")
+      ExcitingUtils.addSink(perfDump, "XSPERF_DUMP")
+      when (perfClean) {
+        counter := 0.U
+      }
       when (printEnable) {  // interval print
         if (acc) {
           XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $next_counter\n")
@@ -127,7 +134,7 @@ object XSPerf extends HasXSParameter {
           XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $perfCnt\n")
         }
       }
-      when (xstrap) {  // summary print
+      when (xstrap || perfDump) {  // summary print
         // dump acc counter by default
         XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $next_counter\n")
       }
diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala
index a1d00e53663b98fcbf8bd951c870162d6c2d98fb..73462c72eb0ff5228cd27aafabc548d263deead8 100644
--- a/src/main/scala/xiangshan/Bundle.scala
+++ b/src/main/scala/xiangshan/Bundle.scala
@@ -515,4 +515,9 @@ class TrapIO extends XSBundle {
   val pc = Output(UInt(VAddrBits.W))
   val cycleCnt = Output(UInt(XLEN.W))
   val instrCnt = Output(UInt(XLEN.W))
+}
+
+class PerfInfoIO extends XSBundle {
+  val clean = Input(Bool())
+  val dump = Input(Bool())
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index 806fc686889bb1a1e01c8a88717b8b148defe595..873a716e56e33d9e3a1bcc72c332224dc6b9bf68 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -109,7 +109,9 @@ case class XSCoreParameters
   PtwL1EntrySize: Int = 16,
   PtwL2EntrySize: Int = 2048, //(256 * 8)
   NumPerfCounters: Int = 16,
-  NrExtIntr: Int = 150
+  NrExtIntr: Int = 150,
+  PerfRealTime: Boolean = false,
+  PerfIntervalBits: Int = 15
 )
 
 trait HasXSParameter {
@@ -192,6 +194,8 @@ trait HasXSParameter {
   val PtwL2EntrySize = core.PtwL2EntrySize
   val NumPerfCounters = core.NumPerfCounters
   val NrExtIntr = core.NrExtIntr
+  val PerfRealTime = core.PerfRealTime
+  val PerfIntervalBits = core.PerfIntervalBits
 
   val instBytes = if (HasCExtension) 2 else 4
   val instOffsetBits = log2Ceil(instBytes)
diff --git a/src/test/scala/top/XSSim.scala b/src/test/scala/top/XSSim.scala
index 9837c5a05d563d4a8b62fff247fd7441f781512b..95752b6889068bb4eec55a6f91b207c40aafb833 100644
--- a/src/test/scala/top/XSSim.scala
+++ b/src/test/scala/top/XSSim.scala
@@ -127,6 +127,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
       val difftest  = new DiffTestIO
       val difftest2 = new DiffTestIO
       val logCtrl = new LogCtrlIO
+      val perfInfo = new PerfInfoIO
       val trap = new TrapIO
       val trap2 = new TrapIO
       val uart = new UARTIO
@@ -135,6 +136,7 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
 
     dontTouch(io.difftest)
     dontTouch(io.logCtrl)
+    dontTouch(io.perfInfo)
     dontTouch(io.trap)
     dontTouch(io.uart)
 
@@ -225,6 +227,13 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
       ExcitingUtils.addSource(timer, "logTimestamp")
     }
 
+    if (env.EnablePerfDebug) {
+      val clean = io.perfInfo.clean
+      val dump = io.perfInfo.dump
+      ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
+      ExcitingUtils.addSource(dump, "XSPERF_DUMP")
+    }
+
     // Check and dispaly all source and sink connections
     ExcitingUtils.fixConnections()
     ExcitingUtils.checkAndDisplay()
@@ -252,6 +261,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
       val difftest  = new DiffTestIO
       val difftest2 = new DiffTestIO
       val logCtrl = new LogCtrlIO
+      val perfInfo = new PerfInfoIO
       val trap = new TrapIO
       val trap2 = new TrapIO
       val uart = new UARTIO
@@ -261,6 +271,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
 
     io.difftest  <> dut.module.io.difftest
     io.logCtrl <> dut.module.io.logCtrl
+    io.perfInfo <> dut.module.io.perfInfo
     io.trap <> dut.module.io.trap
     io.uart <> dut.module.io.uart
     if (!env.FPGAPlatform && env.DualCore) {
@@ -269,8 +280,7 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
     }
     if (axiSim) {
       io.memAXI <> axiSimRam.module.io
-    }
-    else {
+    } else {
       io.memAXI <> DontCare
     }
   }