Merge remote-tracking branch 'origin/master' into opt-dispatch

Makefile

@@ -134,12 +134,23 @@ REF_SO := $(NEMU_HOME)/build/riscv64-nemu-interpreter-so
 $(REF_SO):
 	$(MAKE) -C $(NEMU_HOME) ISA=riscv64 SHARE=1
 
-$(EMU): $(EMU_MK) $(EMU_DEPS) $(EMU_HEADERS) $(REF_SO)
+LOCK = /var/emu/emu.lock
+LOCK_BIN = $(abspath $(BUILD_DIR)/lock-emu)
+
+$(LOCK_BIN): ./scripts/utils/lock-emu.c
+	gcc $^ -o $@
+
+$(EMU): $(EMU_MK) $(EMU_DEPS) $(EMU_HEADERS) $(REF_SO) $(LOCK_BIN)
 	date -R
 ifeq ($(REMOTE),localhost)
 	CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))
 else
-	ssh -tt $(REMOTE) 'CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) -j128 VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))'
+	@echo "try to get emu.lock ..."
+	ssh -tt $(REMOTE) '$(LOCK_BIN) $(LOCK)'
+	@echo "get lock"
+	ssh -tt $(REMOTE) 'CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) -j230 VM_PARALLEL_BUILDS=1 OPT_FAST="-O3" -C $(abspath $(dir $(EMU_MK))) -f $(abspath $(EMU_MK))'
+	@echo "release lock ..."
+	ssh -tt $(REMOTE) 'rm -f $(LOCK)'
 endif
 	date -R
 
@@ -198,6 +209,9 @@ phy_evaluate_atc: vme
 cache:
 	$(MAKE) emu IMAGE=Makefile
 
+release-lock:
+	ssh -tt $(REMOTE) 'rm -f $(LOCK)'
+
 clean:
 	git submodule foreach git clean -fdx
 	git clean -fd

scripts/utils/lock-emu.c

+#include<unistd.h>
+#include<stdio.h>
+#include<stdlib.h>
+#include<sys/stat.h>
+#include<fcntl.h>
+
+int tryLock(char * file){
+    return open(file, O_CREAT | O_EXCL);
+}
+
+int main(int argc, char* argv[]){
+    int fd;
+	if(argc < 2){
+	    printf("arguments are not right!\n");
+		exit(-1);
+	}
+
+    do{
+        fd = tryLock(argv[1]);
+        if(fd > 0) break;
+		printf("there is a job running, waiting ...\n");
+		sleep(10);
+	} while(1);
+
+    return 0;
+}
+

src/main/scala/xiangshan/backend/decode/FPDecoder.scala

@@ -18,7 +18,7 @@ class FPDecoder extends XSModule{
   val s = BitPat(S)
   val d = BitPat(D)
 
-  val default = List(X,X,X,X,N,N,X,X,X)
+  val default = List(X,X,X,N,N,N,X,X,X)
 
   // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt
   val single: Array[(BitPat, List[BitPat])] = Array(

src/main/scala/xiangshan/backend/fu/Alu.scala

@@ -2,7 +2,7 @@ package xiangshan.backend.fu
 
 import chisel3._
 import chisel3.util._
-import utils.{LookupTree, LookupTreeDefault, SignExt, XSDebug, ZeroExt}
+import utils.{LookupTree, LookupTreeDefault, ParallelMux, SignExt, XSDebug, ZeroExt}
 import xiangshan._
 import xiangshan.backend.ALUOpType
 
@@ -20,9 +20,10 @@ class Alu extends FunctionUnit with HasRedirectOut {
   val valid = io.in.valid
 
   val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw)
-  val adderRes = (src1 +& (src2 ^ Fill(XLEN, isAdderSub))) + isAdderSub
+  val addRes = src1 +& src2
+  val subRes = (src1 +& (~src2).asUInt()) + 1.U
   val xorRes = src1 ^ src2
-  val sltu = !adderRes(XLEN)
+  val sltu = !subRes(XLEN)
   val slt = xorRes(XLEN-1) ^ sltu
 
   val shsrc1 = LookupTreeDefault(func, src1, List(
@@ -30,16 +31,23 @@ class Alu extends FunctionUnit with HasRedirectOut {
     ALUOpType.sraw -> SignExt(src1(31,0), 64)
   ))
   val shamt = Mux(ALUOpType.isWordOp(func), src2(4, 0), src2(5, 0))
-  val res = LookupTreeDefault(func(3, 0), adderRes, List(
-    ALUOpType.sll  -> ((shsrc1  << shamt)(XLEN-1, 0)),
+
+  val miscRes = ParallelMux(List(
+    ALUOpType.sll  -> (shsrc1 << shamt)(XLEN-1, 0),
     ALUOpType.slt  -> ZeroExt(slt, XLEN),
     ALUOpType.sltu -> ZeroExt(sltu, XLEN),
     ALUOpType.xor  -> xorRes,
-    ALUOpType.srl  -> (shsrc1  >> shamt),
-    ALUOpType.or   -> (src1  |  src2),
-    ALUOpType.and  -> (src1  &  src2),
-    ALUOpType.sra  -> ((shsrc1.asSInt >> shamt).asUInt)
-  ))
+    ALUOpType.srl  -> (shsrc1 >> shamt),
+    ALUOpType.or   -> (src1 | src2),
+    ALUOpType.and  -> (src1 & src2),
+    ALUOpType.sra  -> (shsrc1.asSInt >> shamt).asUInt
+  ).map(x => (x._1 === func(3, 0), x._2)))
+
+  val res = Mux(ALUOpType.isAddSub(func),
+    Mux(isAdderSub, subRes, addRes),
+    miscRes
+  )
+
   val aluRes = Mux(ALUOpType.isWordOp(func), SignExt(res(31,0), 64), res)
 
   val branchOpTable = List(
@@ -48,10 +56,10 @@ class Alu extends FunctionUnit with HasRedirectOut {
     ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
   )
 
-  val isBranch = uop.cf.brUpdate.pd.isBr// ALUOpType.isBranch(func)
-  val isRVC = uop.cf.brUpdate.pd.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U)
+  val isBranch = ALUOpType.isBranch(func)
+  val isRVC = uop.cf.brUpdate.pd.isRVC
   val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func)
-  val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0)
+  val target = (pc + offset)(VAddrBits-1,0)
   val snpc = Mux(isRVC, pc + 2.U, pc + 4.U)
 
   redirectOutValid := io.out.valid && isBranch

src/main/scala/xiangshan/backend/package.scala

@@ -47,6 +47,10 @@ package object backend {
     def srlw = "b100101".U
     def sraw = "b101101".U
 
+    def isAddSub(func: UInt) = {
+      func === add || func === sub || func === addw || func === subw
+    }
+
     def isWordOp(func: UInt) = func(5)
 
     def beq  = "b010000".U

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -293,7 +293,7 @@ class LoadUnit extends XSModule with HasLoadHelper {
   io.fpout.bits.data := fpRdataHelper(fpLoadOutReg.bits.uop, fpLoadOutReg.bits.data) // recode
   io.fpout.valid := RegNext(fpLoadOut.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect))
 
-  io.lsq.ldout.ready := Mux(refillFpLoad, !fpLoadOut.valid, !intHitLoadOut.valid)
+  io.lsq.ldout.ready := Mux(refillFpLoad, !fpHitLoadOut.valid, !intHitLoadOut.valid)
 
   when(io.ldout.fire()){
     XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc)

src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala

@@ -271,13 +271,9 @@ class NewSbuffer extends XSModule with HasSbufferCst {
   when(io.in(0).fire()){
     when(canMerge(0)){
       mergeWordReq(io.in(0).bits, mergeIdx(0), firstWord)
-      // lruAccessWays(0).valid := true.B
-      // lruAccessWays(0) := Cat(mergeMask(0).reverse)
       XSDebug(p"merge req 0 to line [${mergeIdx(0)}]\n")
     }.elsewhen(firstCanInsert){
       wordReqToBufLine(io.in(0).bits, tags(0), firstInsertIdx, firstWord, true.B)
-      //lruAccessWays(0).valid := true.B
-      // lruAccessWays(0) := Cat(firstInsertMask.reverse)
       XSDebug(p"insert req 0 to line[$firstInsertIdx]\n")
     }
   }
@@ -286,13 +282,9 @@ class NewSbuffer extends XSModule with HasSbufferCst {
   when(io.in(1).fire()){
     when(canMerge(1)){
       mergeWordReq(io.in(1).bits, mergeIdx(1), secondWord)
-      // lruAccessWays(1).valid := true.B
-      // lruAccessWays(1) := Cat(mergeMask(1).reverse)
       XSDebug(p"merge req 1 to line [${mergeIdx(1)}]\n")
     }.elsewhen(secondCanInsert){
       wordReqToBufLine(io.in(1).bits, tags(1), secondInsertIdx, secondWord, !sameTag)
-      //lruAccessWays(1).valid := true.B
-      // lruAccessWays(1) := Cat(PriorityEncoderOH(secondInsertMask).reverse)
       XSDebug(p"insert req 1 to line[$secondInsertIdx]\n")
     }
   }
@@ -375,12 +367,13 @@ class NewSbuffer extends XSModule with HasSbufferCst {
 //
 //  evictionEntry.bits := evictionIdx
 
-  val tagConflict = tagRead(evictionIdx) === tags(0) || tagRead(evictionIdx) === tags(1)
+  val tagConflict = tagRead(evictionIdx) === tags(0) && canMerge(0) && io.in(0).valid ||
+    tagRead(evictionIdx) === tags(1) && canMerge(1) && io.in(1).valid
 
   io.dcache.req.valid :=
     ((do_eviction && sbuffer_state === x_replace) && !tagConflict || (sbuffer_state === x_drain_sbuffer)) &&
     stateVec(evictionIdx)===s_valid &&
-    noSameBlockInflight(evictionIdx) 
+    noSameBlockInflight(evictionIdx)
 
 
   XSDebug(p"1[${((do_eviction && sbuffer_state === x_replace) || (sbuffer_state === x_drain_sbuffer))}] 2[${stateVec(evictionIdx)===s_valid}] 3[${noSameBlockInflight(evictionIdx)}] 4[${!tagConflict}]\n")