dispatch2: refactor regfile ports

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -44,9 +44,9 @@ class Dispatch1 extends XSModule{
                     (io.toLsDq(i).ready  && FuType.isMemExu(io.fromRename(i).bits.ctrl.fuType))
     enq_valid(i) := io.toIntDq(i).valid || io.toFpDq(i).valid || io.toLsDq(i).valid
     io.recv(i) := (enq_ready(i) && enq_valid(i)) || cancelled(i)
-    XSInfo(io.recv(i) && !cancelled(i), "instruction 0x%x accepted by queue %x %x %x\n",
+    XSInfo(io.recv(i) && !cancelled(i), "pc 0x%x accepted by queue %x %x %x\n",
       io.fromRename(i).bits.cf.pc, io.toIntDq(i).valid, io.toFpDq(i).valid, io.toLsDq(i).valid)
-    XSInfo(io.recv(i) && cancelled(i), "instruction 0x%x with brMask %x brTag %x cancelled\n",
+    XSInfo(io.recv(i) && cancelled(i), "pc 0x%x with brMask %x brTag %x cancelled\n",
       io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.brMask, io.redirect.bits.brTag)
   }
 
@@ -64,7 +64,7 @@ class Dispatch1 extends XSModule{
       roqIndexRegValid(i) := false.B
     }
     XSDebug(io.toRoq(i).fire() && !io.recv(i),
-      "instruction 0x%x receives nboq %x but not accepted by queue (and it waits)\n",
+      "pc 0x%x receives nboq %x but not accepted by queue (and it waits)\n",
       io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
   }
 
@@ -93,13 +93,13 @@ class Dispatch1 extends XSModule{
   for (i <- 0 until RenameWidth) {
     io.toRoq(i).bits <> io.fromRename(i).bits
     io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i) && !cancelled(i)
-    XSDebug(io.toRoq(i).fire(), "instruction 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
+    XSDebug(io.toRoq(i).fire(), "pc 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
     if (i > 0) {
       XSWarn(io.toRoq(i).fire() && !io.toRoq(i - 1).ready && io.toRoq(i - 1).valid,
         "roq handshake not continuous %d", i.U)
     }
     io.fromRename(i).ready := all_recv
-    XSDebug(io.fromRename(i).valid, "instruction 0x%x of type %b is in %d-th slot\n",
+    XSDebug(io.fromRename(i).valid, "pc 0x%x of type %b is in %d-th slot\n",
       io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.ctrl.fuType, i.U)
   }
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -24,7 +24,6 @@ class Dispatch2 extends XSModule {
     val enqIQCtrl = Vec(exuConfig.ExuCnt, DecoupledIO(new MicroOp))
     val enqIQData = Vec(exuConfig.ExuCnt, ValidIO(new ExuInput))
   })
-
   // inst indexes for reservation stations
   // append a true.B to avoid PriorityEncode(0000) -> 3
   // if find a target uop, index[2] == 0, else index[2] == 1
@@ -60,26 +59,61 @@ class Dispatch2 extends XSModule {
   }) :+ true.B)
 
   // TODO: currently there's only one load/store reservation station
-  // val load0InstIdx = PriorityEncoder(io.fromLsDq.map(deq => (deq.bits.ctrl.fuType === FuType.ldu)) :+ true.B)
-  val load0InstIdx = PriorityEncoder(io.fromLsDq.map(deq => FuType.isMemExu(deq.bits.ctrl.fuType)) :+ true.B)
+  val load0InstIdx = PriorityEncoder(io.fromLsDq.map(_.bits.ctrl.fuType === FuType.ldu) :+ true.B)
   val load1InstIdx = PriorityEncoder((io.fromLsDq.zipWithIndex map { case (uop, i) =>
     uop.bits.ctrl.fuType === FuType.ldu && i.U > load0InstIdx
   }) :+ true.B)
-  val store0InstIdx = PriorityEncoder(io.fromLsDq.map(_.bits.ctrl.fuType === FuType.stu))
+//  val store0InstIdx = PriorityEncoder(io.fromLsDq.map(_.bits.ctrl.fuType === FuType.stu) :+ true.B)
+  val store0InstIdx = PriorityEncoder(io.fromLsDq.map(deq => FuType.isMemExu(deq.bits.ctrl.fuType)) :+ true.B)
   val store1InstIdx = PriorityEncoder((io.fromLsDq.zipWithIndex map { case (uop, i) =>
     uop.bits.ctrl.fuType === FuType.stu && i.U > store0InstIdx
   }) :+ true.B)
 
   // regfile read ports
   // regfile is sync-read, data can used at the next cycle
-  for (i <- 0 until IntDqDeqWidth) {
-    io.readIntRf(2 * i).addr := io.fromIntDq(i).bits.psrc1
-    io.readIntRf(2 * i + 1).addr := io.fromIntDq(i).bits.psrc2
+  // BRU, MUL0, MUL1 can use the 8 read ports
+  // priority: ALU > BRU > MUL
+  val intExuIndex = WireInit(VecInit(Seq.fill(3)(0.U(2.W))))
+  val aluInstIdxs = Seq(alu0InstIdx, alu1InstIdx, alu2InstIdx, alu3InstIdx)
+  for (i <- 0 until 4) {
+    val readPortSrc = Seq(aluInstIdxs(i), bruInstIdx, mulInstIdx, muldivInstIdx)
+    val wantReadPort = readPortSrc.map(a => !a(2))
+    val readIdxVec = Wire(Vec(4, UInt(2.W)))
+    for (j <- 0 until 4) {
+      readIdxVec(j) := readPortSrc(j)(1, 0)
+    }
+    val deqChoice = PriorityEncoder(wantReadPort)
+    val target = readIdxVec(deqChoice)
+    io.readIntRf(2 * i).addr := io.fromIntDq(target).bits.psrc1
+    io.readIntRf(2 * i + 1).addr := io.fromIntDq(target).bits.psrc2
+    for (j <- 0 until 3) {
+      when (deqChoice === (j + 1).U) {
+        intExuIndex(j) := i.U
+      }
+    }
   }
-  for (i <- 0 until FpDqDeqWidth) {
-    io.readFpRf(3 * i).addr := io.fromFpDq(i).bits.psrc1
-    io.readFpRf(3 * i + 1).addr := io.fromFpDq(i).bits.psrc2
-    io.readFpRf(3 * i + 2).addr := io.fromFpDq(i).bits.psrc3
+
+  // FMAC, FMISC can use the 12 read ports
+  // priority: FMAC > FMISC
+  val fpExuIndex = WireInit(VecInit(Seq.fill(2)(0.U(2.W))))
+  val fmacInstIdxs = Seq(fmac0InstIdx, fmac1InstIdx, fmac2InstIdx, fmac3InstIdx)
+  for (i <- 0 until 4) {
+    val readPortSrc = Seq(fmacInstIdxs(i), fmisc0InstIdx, fmisc1InstIdx)
+    val wantReadPort = readPortSrc.map(a => !a(2))
+    val readIdxVec = Wire(Vec(3, UInt(2.W)))
+    for (j <- 0 until 3) {
+      readIdxVec(j) := readPortSrc(j)(1, 0)
+    }
+    val deqChoice = PriorityEncoder(wantReadPort)
+    val target = readIdxVec(deqChoice)
+    io.readFpRf(3 * i).addr := io.fromFpDq(target).bits.psrc1
+    io.readFpRf(3 * i + 1).addr := io.fromFpDq(target).bits.psrc2
+    io.readFpRf(3 * i + 2).addr := io.fromFpDq(target).bits.psrc3
+    for (j <- 0 until 2) {
+      when (deqChoice === (j + 1).U) {
+        fpExuIndex(j) := i.U
+      }
+    }
   }
   io.readIntRf(2*IntDqDeqWidth).addr := io.fromLsDq(load0InstIdx).bits.psrc1
   io.readIntRf(2*IntDqDeqWidth + 1).addr := io.fromLsDq(load1InstIdx).bits.psrc1
@@ -93,30 +127,35 @@ class Dispatch2 extends XSModule {
   // insert into reservation station
   val instIdxes = Seq(bruInstIdx, alu0InstIdx, alu1InstIdx, alu2InstIdx, alu3InstIdx, mulInstIdx, muldivInstIdx,
     fmac0InstIdx, fmac1InstIdx, fmac2InstIdx, fmac3InstIdx, fmisc0InstIdx, fmisc1InstIdx,
-    load0InstIdx)//, store0InstIdx)
+    /*load0InstIdx, */store0InstIdx)
   io.enqIQCtrl.zipWithIndex map { case (enq, i) =>
     if (i < exuConfig.IntExuCnt) {
       enq.valid := !instIdxes(i)(2) && io.fromIntDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromIntDq(instIdxes(i)(1, 0)).bits
-      enq.bits.src1State := io.intPregRdy((instIdxes(i) << 1).asUInt())
-      enq.bits.src2State := io.intPregRdy((instIdxes(i) << 1).asUInt() + 1.U)
+      val startIndex = if (i == 0) 2.U * intExuIndex(0)
+        else if (i > 4) 2.U * intExuIndex(i - 4)
+        else (2 * (i - 1)).U
+      enq.bits.src1State := io.intPregRdy(startIndex)
+      enq.bits.src2State := io.intPregRdy(startIndex + 1.U)
     }
     else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) {
+      val startIndex = if (i < exuConfig.IntExuCnt + 4) (3 * (i - exuConfig.IntExuCnt)).U
+        else 3.U * fpExuIndex(i - exuConfig.IntExuCnt - 4)
       enq.valid := !instIdxes(i)(2) && io.fromFpDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromFpDq(instIdxes(i)(1, 0)).bits
-      enq.bits.src1State := io.fpPregRdy(instIdxes(i) * 3.U)
-      enq.bits.src2State := io.fpPregRdy(instIdxes(i) * 3.U + 1.U)
-      enq.bits.src3State := io.fpPregRdy(instIdxes(i) * 3.U + 2.U)
+      enq.bits.src1State := io.fpPregRdy(startIndex)
+      enq.bits.src2State := io.fpPregRdy(startIndex + 1.U)
+      enq.bits.src3State := io.fpPregRdy(startIndex + 2.U)
     }
     else {
       enq.valid := !instIdxes(i)(2) && io.fromLsDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromLsDq(instIdxes(i)(1, 0)).bits
       // TODO load and store
-      enq.bits.src1State := Mux(enq.bits.ctrl.fuType === FuType.ldu, io.intPregRdy(8), io.intPregRdy(10))
+      enq.bits.src1State := io.intPregRdy(10)
       enq.bits.src2State := io.intPregRdy(11)
     }
 
-    XSInfo(enq.fire(), "instruction 0x%x with type %b srcState(%d %d %d) enters reservation station %d from %d\n",
+    XSInfo(enq.fire(), "pc 0x%x with type %b srcState(%d %d %d) enters reservation station %d from %d\n",
       enq.bits.cf.pc, enq.bits.ctrl.fuType, enq.bits.src1State, enq.bits.src2State, enq.bits.src3State, i.U, instIdxes(i))
   }
 
@@ -125,10 +164,10 @@ class Dispatch2 extends XSModule {
     io.fromIntDq(i).ready := (io.enqIQCtrl.zipWithIndex map {case (rs, j) =>
       (rs.ready && instIdxes(j) === i.U && (j < exuConfig.IntExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    XSInfo(io.fromIntDq(i).fire(), "instruction 0x%x leaves Int dispatch queue with nroq %d\n",
+    XSInfo(io.fromIntDq(i).fire(), "pc 0x%x leaves Int dispatch queue with nroq %d\n",
       io.fromIntDq(i).bits.cf.pc, io.fromIntDq(i).bits.roqIdx)
     XSDebug(io.fromIntDq(i).valid && !io.fromIntDq(i).ready,
-      "instruction 0x%x waits at Int dispatch queue with index %d\n",
+      "pc 0x%x waits at Int dispatch queue with index %d\n",
       io.fromIntDq(i).bits.cf.pc, i.U)
   }
   for (i <- 0 until FpDqDeqWidth) {
@@ -136,10 +175,10 @@ class Dispatch2 extends XSModule {
       (rs.ready && instIdxes(j) === i.U
         && (j >= exuConfig.IntExuCnt && j < exuConfig.IntExuCnt + exuConfig.FpExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    XSInfo(io.fromFpDq(i).fire(), "instruction 0x%x leaves Fp dispatch queue with nroq %d\n",
+    XSInfo(io.fromFpDq(i).fire(), "pc 0x%x leaves Fp dispatch queue with nroq %d\n",
       io.fromFpDq(i).bits.cf.pc, io.fromFpDq(i).bits.roqIdx)
     XSDebug(io.fromFpDq(i).valid && !io.fromFpDq(i).ready,
-      "instruction 0x%x waits at Fp dispatch queue with index %d\n",
+      "pc 0x%x waits at Fp dispatch queue with index %d\n",
       io.fromFpDq(i).bits.cf.pc, i.U)
   }
   for (i <- 0 until LsDqDeqWidth) {
@@ -147,84 +186,56 @@ class Dispatch2 extends XSModule {
       (rs.ready && instIdxes(j) === i.U
         && (j >= exuConfig.IntExuCnt + exuConfig.FpExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    XSInfo(io.fromLsDq(i).fire(), "instruction 0x%x leaves Ls dispatch queue with nroq %d\n",
+    XSInfo(io.fromLsDq(i).fire(), "pc 0x%x leaves Ls dispatch queue with nroq %d\n",
       io.fromLsDq(i).bits.cf.pc, io.fromLsDq(i).bits.roqIdx)
     XSDebug(io.fromLsDq(i).valid && !io.fromLsDq(i).ready,
-      "instruction 0x%x waits at Ls dispatch queue with index %d\n",
+      "pc 0x%x waits at Ls dispatch queue with index %d\n",
       io.fromLsDq(i).bits.cf.pc, i.U)
   }
 
-  // next stage: insert data
-  val data_valid = Reg(Vec(exuConfig.ExuCnt, Bool()))
-  val uop_reg = Reg(Vec(exuConfig.ExuCnt, new MicroOp))
-  // indexes can be one-hot to reduce overhead
-  val index_reg = Reg(Vec(exuConfig.ExuCnt, UInt(instIdxes(0).getWidth.W)))
-  // types: 0 for Int, 1 for Fp, 2 for empty
   // TODO: store needs data from FpRegfile
-  val src1Type = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) 0.U
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) 1.U
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 0.U
-    else 0.U // TODO: Mux(uop_reg(i).ctrl)
-  )
-  val src2Type = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) 0.U
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) 1.U
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 2.U
-    else 0.U
-  )
-  val src3Type = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) 2.U
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) 1.U
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 2.U
-    else 2.U
-  )
-  val src1Index = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) (index_reg(i) << 1).asUInt()
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) (index_reg(i) * 3.U).asUInt()
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 8.U
-    else 10.U
-  )
-  val src2Index = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) (index_reg(i) << 1).asUInt() + 1.U
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) index_reg(i) * 3.U + 1.U
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 0.U
-    else 11.U
-  )
-  val src3Index = (0 until exuConfig.ExuCnt).map(i =>
-    if (i < exuConfig.IntExuCnt) 0.U
-    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) index_reg(i) * 3.U + 2.U
-    else if (i == exuConfig.IntExuCnt + exuConfig.FpExuCnt) 0.U
-    else 0.U
-  )
+  val intExuIndexReg = Reg(Vec(3, UInt(2.W)))
+  val fpExuIndexReg = Reg(Vec(2, UInt(2.W)))
+  (0 until 3).map(i => intExuIndexReg(i) := intExuIndex(i))
+  (0 until 2).map(i => fpExuIndexReg(i) := fpExuIndex(i))
   for (i <- 0 until exuConfig.ExuCnt) {
-    data_valid(i) := io.enqIQCtrl(i).fire()
-    uop_reg(i) := io.enqIQCtrl(i).bits
-    index_reg(i) := instIdxes(i)
+    io.enqIQData(i).valid := DontCare
+    io.enqIQData(i).bits := DontCare
 
-    io.enqIQData(i).valid := data_valid(i)
-    io.enqIQData(i).bits.uop := uop_reg(i)
-//    io.enqIQData(i).bits.uop.src1State := Mux(src1Type(i)(1), SrcState.rdy,
-//      Mux(src1Type(i)(0), io.intPregRdy(src1Index(i)), io.fpPregRdy(src1Index(i))))
-//    io.enqIQData(i).bits.uop.src2State := Mux(src2Type(i)(1), SrcState.rdy,
-//      Mux(src2Type(i)(0), io.intPregRdy(src2Index(i)), io.fpPregRdy(src2Index(i))))
-//    io.enqIQData(i).bits.uop.src3State := Mux(src3Type(i)(1), SrcState.rdy,
-//      Mux(src3Type(i)(0), io.intPregRdy(src3Index(i)), io.fpPregRdy(src3Index(i))))
-    val src1 = Mux(src1Type(i)(1), io.readFpRf(src1Index(i)).data, io.readIntRf(src1Index(i)).data)
-    io.enqIQData(i).bits.src1 := Mux(io.enqIQData(i).bits.uop.ctrl.src1Type === SrcType.pc,
-        io.enqIQData(i).bits.uop.cf.pc, Mux(index_reg(i)(2), 0.U, src1))
-    val src2 = Mux(src2Type(i)(1), io.readFpRf(src2Index(i)).data, io.readIntRf(src2Index(i)).data)
-    io.enqIQData(i).bits.src2 := Mux(io.enqIQData(i).bits.uop.ctrl.src2Type === SrcType.imm,
-      io.enqIQData(i).bits.uop.ctrl.imm, Mux(index_reg(i)(2), 0.U, src2))
-    val src3 = Mux(src3Type(i)(1), io.readFpRf(src3Index(i)).data, io.readIntRf(src3Index(i)).data)
-    io.enqIQData(i).bits.src3 := Mux(index_reg(i)(2), 0.U, src3)
+    val srcIndex = Wire(Vec(3, UInt(4.W)))
+    if (i < exuConfig.IntExuCnt) {
+      val startIndex = if (i == 0)2.U * intExuIndexReg(0)
+        else if (i > 4) 2.U * intExuIndexReg(i - 4)
+        else (2 * (i - 1)).U
+      io.enqIQData(i).bits.src1 := io.readIntRf(startIndex).data
+      io.enqIQData(i).bits.src2 := io.readIntRf(startIndex + 1.U).data
+      srcIndex(0) := startIndex
+      srcIndex(1) := startIndex + 1.U
+      srcIndex(2) := 0.U
+    }
+    else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) {
+      val startIndex = if (i < exuConfig.IntExuCnt + 4) (3 * (i-exuConfig.IntExuCnt)).U
+        else 3.U * fpExuIndexReg(i - exuConfig.IntExuCnt - 4)
+      io.enqIQData(i).bits.src1 := io.readFpRf(startIndex).data
+      io.enqIQData(i).bits.src2 := io.readFpRf(startIndex + 1.U).data
+      io.enqIQData(i).bits.src3 := io.readFpRf(startIndex + 2.U).data
+      srcIndex(0) := startIndex
+      srcIndex(1) := startIndex + 1.U
+      srcIndex(2) := startIndex + 2.U
+    }
+    else {
+      io.enqIQData(i).bits.src1 := io.readIntRf(10).data
+      io.enqIQData(i).bits.src2 := io.readIntRf(11).data
+      srcIndex(0) := 10.U
+      srcIndex(1) := 11.U
+      srcIndex(2) := 0.U
+    }
 
     XSDebug(io.enqIQData(i).valid,
-      "instruction 0x%x reads operands from (%d, %d, %d, %x), (%d, %d, %d, %x), (%d, %d, %d, %x)\n",
+      "pc 0x%x reads operands from (%d, %d, %x), (%d, %d, %x), (%d, %d, %x)\n",
       io.enqIQData(i).bits.uop.cf.pc,
-      src1Type(i), src1Index(i), io.enqIQData(i).bits.uop.psrc1, io.enqIQData(i).bits.src1,
-      src2Type(i), src2Index(i), io.enqIQData(i).bits.uop.psrc2, io.enqIQData(i).bits.src2,
-      src3Type(i), src3Index(i), io.enqIQData(i).bits.uop.psrc3, io.enqIQData(i).bits.src3)
+      srcIndex(0), io.enqIQData(i).bits.uop.psrc1, io.enqIQData(i).bits.src1,
+      srcIndex(1), io.enqIQData(i).bits.uop.psrc2, io.enqIQData(i).bits.src2,
+      srcIndex(2), io.enqIQData(i).bits.uop.psrc3, io.enqIQData(i).bits.src3)
   }
-
 }