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体验新版 GitCode,发现更多精彩内容 >>
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64348ccc
编写于
6月 29, 2020
作者:
Y
Yinan Xu
提交者:
GitHub
6月 29, 2020
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差异文件
Merge pull request #71 from RISCVERS/fix-busytable-bug
Rename: use walk recovery busytable
上级
9bb97e7f
75bc8863
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
6 addition
and
3 deletion
+6
-3
src/main/scala/xiangshan/backend/rename/BusyTable.scala
src/main/scala/xiangshan/backend/rename/BusyTable.scala
+2
-2
src/main/scala/xiangshan/backend/rename/Rename.scala
src/main/scala/xiangshan/backend/rename/Rename.scala
+4
-1
未找到文件。
src/main/scala/xiangshan/backend/rename/BusyTable.scala
浏览文件 @
64348ccc
...
@@ -10,8 +10,8 @@ class BusyTable extends XSModule {
...
@@ -10,8 +10,8 @@ class BusyTable extends XSModule {
val
flush
=
Input
(
Bool
())
val
flush
=
Input
(
Bool
())
// set preg state to busy
// set preg state to busy
val
allocPregs
=
Vec
(
RenameWidth
,
Flipped
(
ValidIO
(
UInt
(
PhyRegIdxWidth
.
W
))))
val
allocPregs
=
Vec
(
RenameWidth
,
Flipped
(
ValidIO
(
UInt
(
PhyRegIdxWidth
.
W
))))
// set preg state to ready
// set preg state to ready
(write back regfile + roq walk)
val
wbPregs
=
Vec
(
NRWritePorts
,
Flipped
(
ValidIO
(
UInt
(
PhyRegIdxWidth
.
W
))))
val
wbPregs
=
Vec
(
NRWritePorts
+
CommitWidth
,
Flipped
(
ValidIO
(
UInt
(
PhyRegIdxWidth
.
W
))))
// read preg state
// read preg state
val
rfReadAddr
=
Vec
(
NRReadPorts
,
Input
(
UInt
(
PhyRegIdxWidth
.
W
)))
val
rfReadAddr
=
Vec
(
NRReadPorts
,
Input
(
UInt
(
PhyRegIdxWidth
.
W
)))
val
pregRdy
=
Vec
(
NRReadPorts
,
Output
(
Bool
()))
val
pregRdy
=
Vec
(
NRReadPorts
,
Output
(
Bool
()))
...
...
src/main/scala/xiangshan/backend/rename/Rename.scala
浏览文件 @
64348ccc
...
@@ -112,6 +112,9 @@ class Rename extends XSModule {
...
@@ -112,6 +112,9 @@ class Rename extends XSModule {
rat
.
specWritePorts
(
i
).
addr
:=
Mux
(
specWen
,
uops
(
i
).
ctrl
.
ldest
,
io
.
roqCommits
(
i
).
bits
.
uop
.
ctrl
.
ldest
)
rat
.
specWritePorts
(
i
).
addr
:=
Mux
(
specWen
,
uops
(
i
).
ctrl
.
ldest
,
io
.
roqCommits
(
i
).
bits
.
uop
.
ctrl
.
ldest
)
rat
.
specWritePorts
(
i
).
wdata
:=
Mux
(
specWen
,
freeList
.
pdests
(
i
),
io
.
roqCommits
(
i
).
bits
.
uop
.
old_pdest
)
rat
.
specWritePorts
(
i
).
wdata
:=
Mux
(
specWen
,
freeList
.
pdests
(
i
),
io
.
roqCommits
(
i
).
bits
.
uop
.
old_pdest
)
busyTable
.
wbPregs
(
NRWritePorts
+
i
).
valid
:=
walkWen
busyTable
.
wbPregs
(
NRWritePorts
+
i
).
bits
:=
io
.
roqCommits
(
i
).
bits
.
uop
.
pdest
XSInfo
(
walkWen
,
XSInfo
(
walkWen
,
{
if
(
fp
)
p
"fp"
else
p
"int "
}
+
p
"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}"
+
{
if
(
fp
)
p
"fp"
else
p
"int "
}
+
p
"walk: pc:${Hexadecimal(io.roqCommits(i).bits.uop.cf.pc)}"
+
p
" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
p
" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
...
@@ -169,7 +172,7 @@ class Rename extends XSModule {
...
@@ -169,7 +172,7 @@ class Rename extends XSModule {
def
updateBusyTable
(
fp
:
Boolean
)
=
{
def
updateBusyTable
(
fp
:
Boolean
)
=
{
val
wbResults
=
if
(
fp
)
io
.
wbFpResults
else
io
.
wbIntResults
val
wbResults
=
if
(
fp
)
io
.
wbFpResults
else
io
.
wbIntResults
val
busyTable
=
if
(
fp
)
fpBusyTable
else
intBusyTable
val
busyTable
=
if
(
fp
)
fpBusyTable
else
intBusyTable
for
((
wb
,
setPhyRegRdy
)
<-
wbResults
.
zip
(
busyTable
.
wbPregs
)){
for
((
wb
,
setPhyRegRdy
)
<-
wbResults
.
zip
(
busyTable
.
wbPregs
.
take
(
NRWritePorts
)
)){
setPhyRegRdy
.
valid
:=
wb
.
valid
&&
needDestReg
(
fp
,
wb
.
bits
.
uop
)
setPhyRegRdy
.
valid
:=
wb
.
valid
&&
needDestReg
(
fp
,
wb
.
bits
.
uop
)
setPhyRegRdy
.
bits
:=
wb
.
bits
.
uop
.
pdest
setPhyRegRdy
.
bits
:=
wb
.
bits
.
uop
.
pdest
}
}
...
...
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