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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
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95c56213
编写于
5月 26, 2023
作者:
X
Xuan Hu
浏览文件
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电子邮件补丁
差异文件
vector: add mask-tail genenerator for byte data
上级
2df0274e
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
128 addition
and
0 deletion
+128
-0
src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
...n/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
+83
-0
src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala
...ala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala
+45
-0
未找到文件。
src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
0 → 100644
浏览文件 @
95c56213
package
xiangshan.backend.fu.vector
import
chipsalliance.rocketchip.config.Parameters
import
chisel3._
import
chisel3.util._
import
xiangshan.backend.fu.vector.Bundles.
{
VSew
,
Vl
}
import
xiangshan.backend.fu.vector.utils.
{
MaskExtractor
,
UIntToContLow0s
,
UIntToContLow1s
}
import
_root_.utils.XSDebug
import
yunsuan.vector.SewOH
class
ByteMaskTailGenIO
(
vlen
:
Int
)(
implicit
p
:
Parameters
)
extends
Bundle
{
private
val
numBytes
=
vlen
/
8
private
val
elemIdxWidth
=
log2Up
(
numBytes
+
1
)
// if numBytes is 16, begin and end should contains 0~16
println
(
s
"elemIdxWidth: $elemIdxWidth"
)
val
in
=
Input
(
new
Bundle
{
val
begin
=
UInt
(
elemIdxWidth
.
W
)
val
end
=
UInt
(
elemIdxWidth
.
W
)
val
vma
=
Bool
()
val
vta
=
Bool
()
val
vsew
=
VSew
()
val
maskUsed
=
UInt
(
numBytes
.
W
)
})
val
out
=
Output
(
new
Bundle
{
val
keepEn
=
UInt
(
numBytes
.
W
)
val
agnosticEn
=
UInt
(
numBytes
.
W
)
})
val
debugOnly
=
Output
(
new
Bundle
{
val
startBytes
=
UInt
()
val
vlBytes
=
UInt
()
val
prestartEn
=
UInt
()
val
activeEn
=
UInt
()
val
tailEn
=
UInt
()
val
maskEn
=
UInt
()
val
maskAgnosticEn
=
UInt
()
val
tailAgnosticEn
=
UInt
()
val
agnosticEn
=
UInt
()
})
}
class
ByteMaskTailGen
(
vlen
:
Int
)(
implicit
p
:
Parameters
)
extends
Module
{
require
(
isPow2
(
vlen
))
private
val
numBytes
=
vlen
/
8
private
val
byteWidth
=
log2Up
(
numBytes
)
// vlen=128, numBytes=16, byteWidth=log2(16)=4
println
(
s
"numBytes: ${numBytes}, byteWidth: ${byteWidth}"
)
val
io
=
IO
(
new
ByteMaskTailGenIO
(
vlen
))
private
val
eewOH
=
SewOH
(
io
.
in
.
vsew
).
oneHot
private
val
startBytes
=
Mux1H
(
eewOH
,
Seq
.
tabulate
(
4
)(
x
=>
io
.
in
.
begin
(
byteWidth
-
x
,
0
)
<<
x
)).
asUInt
private
val
vlBytes
=
Mux1H
(
eewOH
,
Seq
.
tabulate
(
4
)(
x
=>
io
.
in
.
end
(
byteWidth
-
x
,
0
)
<<
x
)).
asUInt
private
val
prestartEn
=
UIntToContLow1s
(
startBytes
,
numBytes
)
private
val
activeEn
=
UIntToContLow0s
(
startBytes
,
numBytes
)
&
UIntToContLow1s
(
vlBytes
,
numBytes
)
private
val
tailEn
=
UIntToContLow0s
(
vlBytes
,
numBytes
)
private
val
maskEn
=
MaskExtractor
(
vlen
)(
io
.
in
.
maskUsed
,
io
.
in
.
vsew
)
private
val
maskOffEn
=
(~
maskEn
).
asUInt
private
val
maskAgnosticEn
=
Mux
(
io
.
in
.
vma
,
maskOffEn
,
0.
U
)
private
val
tailAgnosticEn
=
Mux
(
io
.
in
.
vta
,
tailEn
,
0.
U
)
private
val
keepEn
=
activeEn
&
maskEn
private
val
agnosticEn
=
maskAgnosticEn
|
tailAgnosticEn
io
.
out
.
keepEn
:=
keepEn
io
.
out
.
agnosticEn
:=
agnosticEn
io
.
debugOnly
.
startBytes
:=
startBytes
io
.
debugOnly
.
vlBytes
:=
vlBytes
io
.
debugOnly
.
prestartEn
:=
prestartEn
io
.
debugOnly
.
activeEn
:=
activeEn
io
.
debugOnly
.
tailEn
:=
tailEn
io
.
debugOnly
.
maskEn
:=
maskEn
io
.
debugOnly
.
maskAgnosticEn
:=
maskAgnosticEn
io
.
debugOnly
.
tailAgnosticEn
:=
tailAgnosticEn
io
.
debugOnly
.
agnosticEn
:=
agnosticEn
}
src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala
0 → 100644
浏览文件 @
95c56213
package
xiangshan.backend.fu.vector
import
chisel3._
import
chiseltest._
import
org.scalatest.flatspec.AnyFlatSpec
import
org.scalatest.matchers.must.Matchers
import
top.DefaultConfig
import
xiangshan.backend.fu.vector.Bundles.VSew
import
xiangshan.
{
XSCoreParameters
,
XSCoreParamsKey
}
class
ByteMaskTailGenTest
extends
AnyFlatSpec
with
ChiselScalatestTester
with
Matchers
{
println
(
"Generating the ByteMaskTailGen hardware"
)
val
defaultConfig
=
(
new
DefaultConfig
).
alterPartial
({
case
XSCoreParamsKey
=>
XSCoreParameters
()
})
emitVerilog
(
new
ByteMaskTailGen
(
128
)(
defaultConfig
),
Array
(
"--target-dir"
,
"build/ByteMaskTailGen"
))
println
(
"test start"
)
behavior
of
"ByteMaskTailGen"
it
should
"run"
in
{
test
(
new
ByteMaskTailGen
(
128
)(
defaultConfig
)).
withAnnotations
(
Seq
(
VerilatorBackendAnnotation
))
{
m
:
ByteMaskTailGen
=>
m
.
io
.
in
.
begin
.
poke
(
2.
U
)
m
.
io
.
in
.
end
.
poke
(
7.
U
)
m
.
io
.
in
.
vma
.
poke
(
false
.
B
)
m
.
io
.
in
.
vta
.
poke
(
false
.
B
)
m
.
io
.
in
.
vsew
.
poke
(
VSew
.
e8
)
m
.
io
.
in
.
maskUsed
.
poke
(
"b0101_0101_0101_0101"
.
U
)
println
(
"startBytes: "
+
m
.
io
.
debugOnly
.
startBytes
.
peek
().
litValue
.
toInt
)
println
(
"vlBytes: "
+
m
.
io
.
debugOnly
.
vlBytes
.
peek
().
litValue
.
toInt
)
println
(
"prestartEn: "
+
m
.
io
.
debugOnly
.
prestartEn
.
peek
().
litValue
.
toString
(
2
))
println
(
"activeEn: "
+
m
.
io
.
debugOnly
.
activeEn
.
peek
().
litValue
.
toString
(
2
))
println
(
"tailEn: "
+
m
.
io
.
debugOnly
.
tailEn
.
peek
().
litValue
.
toString
(
2
))
println
(
"maskEn: "
+
m
.
io
.
debugOnly
.
maskEn
.
peek
().
litValue
.
toString
(
2
))
println
(
"keepEn: "
+
m
.
io
.
out
.
keepEn
.
peek
().
litValue
.
toString
(
2
))
println
(
"agnosticEn: "
+
m
.
io
.
out
.
agnosticEn
.
peek
().
litValue
.
toString
(
2
))
}
println
(
"test done"
)
}
}
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