Merge pull request #65 from RISCVERS/bru

BRU: add BRU which only supports jal/jalr and its log info

src/main/scala/xiangshan/backend/exu/Bru.scala

+package xiangshan.backend.exu
+
+import chisel3._
+import chisel3.util._
+import xiangshan._
+import xiangshan.FuType._
+import xiangshan.utils._
+import xiangshan.backend.regfile.RfWritePort
+import xiangshan.backend.BRUOpType
+
+// NOTE: BRUOpType is at backend/package.scala
+
+class Bru extends Exu(FuType.bru.litValue(), writeFpRf = true) {
+  override def toString: String = "Bru"
+
+  val (iovalid, src1, offset, func, pc, uop) = (io.in.valid, io.in.bits.src1, io.in.bits.uop.ctrl.imm, io.in.bits.uop.ctrl.fuOpType, SignExt(io.in.bits.uop.cf.pc, AddrBits), io.in.bits.uop)
+
+  val redirectHit = (io.redirect.valid &&
+    ((UIntToOH(io.redirect.bits.brTag) & uop.brMask).orR || io.redirect.bits.isException))
+  val valid = iovalid && !redirectHit
+
+  val isCSR = BRUOpType.isCSR(func)
+  val isFMV = BRUOpType.isFMV(func)
+  val isMOU = BRUOpType.isMOU(func)
+  val isJUMP = BRUOpType.isJUMP(func)
+
+  // CSR
+
+  // FMV
+
+  // MOU
+
+  // JUMP
+  val isRVC = uop.cf.isRVC
+  val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
+  val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
+
+  io.out.bits.redirect.valid := valid && isJUMP
+  io.out.bits.redirect.bits.target := target
+  io.out.bits.redirect.bits.brTag := uop.brTag
+  io.out.bits.redirect.bits.isException := false.B
+  io.out.bits.redirect.bits.roqIdx := uop.roqIdx
+  io.out.bits.redirect.bits.freelistAllocPtr := uop.freelistAllocPtr
+
+  // Output
+  val resCSR = WireInit(0.U(XLEN.W)) // TODO: implement it
+  val resFMV = WireInit(0.U(XLEN.W)) // TODO: implement it
+  val resMOU = WireInit(0.U(XLEN.W)) // TODO: implement it
+  val resJMP = pcDelaySlot
+  val res = ParallelMux(
+    VecInit(isCSR,  isFMV,  isMOU,  isJUMP) zip
+    VecInit(resCSR, resFMV, resMOU, resJMP)
+  )
+
+  io.in.ready := io.out.ready
+  io.out.valid := valid // TODO: CSR/MOU/FMV may need change it
+  io.out.bits.uop <> io.in.bits.uop
+  io.out.bits.data := res
+
+  io.dmem <> DontCare
+  io.out.bits.debug.isMMIO := DontCare
+
+  // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it
+  XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n",
+    io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag, uop.brMask)
+  XSDebug(io.in.valid && isCSR, "src1:%x offset:%x func:%b type:CSR pc:%x\n", src1, offset, func, pc)
+  XSDebug(io.in.valid && isFMV, "src1:%x offset:%x func:%b type:FMV pc:%x\n", src1, offset, func, pc)
+  XSDebug(io.in.valid && isMOU, "src1:%x offset:%x func:%b type:MOU pc:%x\n", src1, offset, func, pc)
+  XSDebug(io.in.valid && isJUMP, "src1:%x offset:%x func:%b type:JUMP pc:%x\n", src1, offset, func, pc)
+  XSDebug(io.in.valid, "Res:%x` CsrRes:%x FMV:%x Mou:%x Jmp:%x\n", res, resCSR, resFMV, resMOU, resJMP)
+}
\ No newline at end of file

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -39,10 +39,6 @@ abstract class Exu
   val io = IO(new ExuIO)
 }
 
-class Bru extends Exu(FuType.bru.litValue(), writeFpRf = true) with NeedImpl{
-  override def toString: String = "Bru"
-}
-
 class Mul extends Exu(FuType.mul.litValue()) with NeedImpl{
   override def toString: String = "Mul"
 }

src/main/scala/xiangshan/backend/package.scala

@@ -5,24 +5,38 @@ import chisel3.util._
 
 package object backend {
 
-  // jal csr mov
+  // jal csr move(x2f) mou
   object BRUOpType {
-    // 1. jal
-    def jal  = "b011000".U
-    def jalr = "b011010".U
-    // def cjalr= "b111010".U // pc + 2 instead of 4
-
-    // 2. csr
-    def jmp  = "b000".U
-    def wrt  = "b001".U
-    def set  = "b010".U
-    def clr  = "b011".U
-    def wrti = "b101".U
-    def seti = "b110".U
-    def clri = "b111".U
-
-    // todo: 3. mov
-//    def pcPlus2(func: UInt) = func(5)//[important]
+    // [2bit:Type]: 00:csr 01:move(x2f) mou(fence.i,etc) jump
+    // 0. csr
+    def jmp  = "b00_000".U
+    def wrt  = "b00_001".U
+    def set  = "b00_010".U
+    def clr  = "b00_011".U
+    def wrti = "b00_101".U
+    def seti = "b00_110".U
+    def clri = "b00_111".U
+
+    // 1. move(x2f)
+    // FIXME: temp decode, should be fixed when use it
+    def fmv_w_x = "b01_000".U
+    def fmv_d_x = "b01_001".U
+
+    // 2. mou
+    def fence  = "b01_000".U
+    def fencei = "b01_001".U
+    def sfence_vma = "b01_010".U
+
+    // 3. jump
+    def jal  = "b11_000".U
+    def jalr = "b11_010".U
+    def call = "b11_011".U
+    def ret  = "b11_100".U
+
+    def isCSR(func: UInt) = func(4,3)===0.U
+    def isFMV(func: UInt) = func(4,3)===1.U
+    def isMOU(func: UInt) = func(4,3)===2.U // TODO: change its name
+    def isJUMP(func: UInt) = func(4,3)===3.U
   }
 
 
@@ -44,6 +58,12 @@ package object backend {
     def srlw = "b100101".U
     def sraw = "b101101".U
 
+    def isWordOp(func: UInt) = func(5)
+
+    // TODO: move jal/jalr/call/ret from ALU to BRU&CSR
+    def jal  = "b011000".U
+    def jalr = "b011010".U
+    // def cjalr= "b111010".U // pc + 2 instead of 4
     def beq  = "b010000".U
     def bne  = "b010001".U
     def blt  = "b010100".U
@@ -51,16 +71,14 @@ package object backend {
     def bltu = "b010110".U
     def bgeu = "b010111".U
 
-    def isWordOp(func: UInt) = func(5)
-
     // for RAS
-//    def call = "b011100".U
-//    def ret  = "b011110".U
+    def call = "b011100".U
+    def ret  = "b011110".U
 
-//    def isBru(func: UInt) = func(4)//[important]
-    def pcPlus2(func: UInt) = func(5)//[important]
-    def isBranch(func: UInt) = !func(3)
-//    def isJump(func: UInt) = isBru(func) && !isBranch(func)
+    // def pcPlus2(func: UInt) = func(5)//[important]
+    def isBranch(func: UInt) = func(4,3)===2.U
+    def isBru(func: UInt) = func(4)
+    def isJump(func: UInt) = func(4,3)===3.U//isBru(func) && !isBranch(func)
     def getBranchType(func: UInt) = func(2, 1)
     def isBranchInvert(func: UInt) = func(0)
   }