Merge pull request #64 from RISCVERS/roq-writeback-log

roq, writeback: add log

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -90,8 +90,8 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, name: String) extends X
 
   XSDebug(num_deq > 0.U, name + ": num_deq = %d, head = (%d -> %d)\n",
       num_deq, head, (head + num_deq) % size.U)
-  XSDebug(num_enq > 0.U, name + "] num_enq = %d, tail = (%d -> %d)\n",
+  XSDebug(num_enq > 0.U, name + ": num_enq = %d, tail = (%d -> %d)\n",
       num_enq, tail, (tail + num_enq) % size.U)
-  XSDebug(valid_entries > 0.U, name + "] valid_entries = %d, head = (%d, %d), tail = (%d, %d), \n",
+  XSDebug(valid_entries > 0.U, name + ": valid_entries = %d, head = (%d, %d), tail = (%d, %d), \n",
       valid_entries, head_direction, head, tail_direction, tail)
-}
\ No newline at end of file
+}

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.FuType._
+import xiangshan.utils.XSInfo
 
 case class ExuConfig
 (
@@ -127,4 +128,10 @@ class WriteBackArbMtoN(m: Int, n: Int) extends XSModule {
     io.out(i).bits := io.in(i).bits
     io.in(i).ready := true.B
   }
+
+  for (i <- 0 until n) {
+    XSInfo(io.out(i).valid, "out(%d) pc(0x%x) writebacks 0x%x to pdest(%d) ldest(%d)\n", i.U, io.out(i).bits.uop.cf.pc,
+      io.out(i).bits.data, io.out(i).bits.uop.pdest, io.out(i).bits.uop.ctrl.ldest)
+  }
+
 }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -70,14 +70,14 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       writebacked(io.exeWbResults(i).bits.uop.roqIdx) := true.B
       exuData(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.data
       exuDebug(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.debug
+      XSInfo("0x%x writebacks 0x%x\n", io.exeWbResults(i).bits.uop.cf.pc, io.exeWbResults(i).bits.data)
     }
   }
   val firedWriteback = VecInit((0 until exuConfig.ExuCnt).map(io.exeWbResults(_).fire())).asUInt
-  when(PopCount(firedWriteback) > 0.U){
-    XSInfo("writebacked %d insts\n", PopCount(firedWriteback))
-  }
+  XSInfo(PopCount(firedWriteback) > 0.U, "writebacked %d insts\n", PopCount(firedWriteback))
   for(i <- 0 until exuConfig.ExuCnt){
-    XSInfo("writebacked pc %x wen %d data %d\n", microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc, microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, io.exeWbResults(i).bits.data)
+    XSInfo(io.exeWbResults(i).valid, "writebacked pc 0x%x wen %d data 0x%x\n", microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc,
+      microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, io.exeWbResults(i).bits.data)
   }
 
   // Commit uop to Rename
@@ -107,20 +107,16 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   io.scommit := PopCount(validScommit.asUInt)
 
   XSInfo(retireCounter > 0.U, "retired %d insts\n", retireCounter)
-  XSInfo("")
-  XSInfo(){
-    printf("retired pcs are: ")
-    for(i <- 0 until CommitWidth){
-      when(io.commits(i).valid){ printf("%d:0x%x ", ringBufferTail+i.U, microOp(ringBufferTail+i.U).cf.pc) }
-    }
-    printf("\n")
+  for(i <- 0 until CommitWidth) {
+      XSInfo(io.commits(i).valid, "retired pc at commmit(%d) is: %d 0x%x\n",
+        i.U, ringBufferTail+i.U, microOp(ringBufferTail+i.U).cf.pc)
   }
 
   val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_)
 
-  when(state===s_walk){
+  when(state===s_walk) {
     //exit walk state when all roq entry is commited
-    when(walkFinished){
+    when(walkFinished) {
       state := s_idle
     }
     ringBufferWalkExtended := ringBufferWalkExtended + CommitWidth.U