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7157d580
编写于
2月 20, 2021
作者:
Z
zhanglinjuan
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电子邮件补丁
差异文件
L1plusPrefetcher: add latch of l1+prefetch req for timing optimization
上级
2118190b
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
28 addition
and
8 deletion
+28
-8
src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
...ain/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
+28
-8
未找到文件。
src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
浏览文件 @
7157d580
...
...
@@ -24,6 +24,23 @@ class L1plusPrefetcher extends PrefetchModule {
val
mem_grant
=
Flipped
(
DecoupledIO
(
new
L1plusCacheResp
))
})
def
latch_decoupled
[
T
<:
Data
](
source
:
DecoupledIO
[
T
],
sink
:
DecoupledIO
[
T
])
=
{
val
latch
=
Reg
(
source
.
bits
.
cloneType
.
asInstanceOf
[
T
])
val
valid
=
RegInit
(
false
.
B
)
when
(
sink
.
fire
())
{
valid
:=
false
.
B
}
when
(
source
.
fire
())
{
valid
:=
true
.
B
latch
:=
source
.
bits
}
sink
.
valid
:=
valid
sink
.
bits
:=
latch
source
.
ready
:=
!
valid
||
sink
.
fire
()
}
if
(
l1plusPrefetcherParameters
.
enable
&&
l1plusPrefetcherParameters
.
_type
==
"stream"
)
{
val
streamParams
=
l1plusPrefetcherParameters
.
streamParams
val
pft
=
Module
(
new
StreamPrefetch
(
streamParams
))
...
...
@@ -33,11 +50,13 @@ class L1plusPrefetcher extends PrefetchModule {
pft
.
io
.
train
.
bits
.
miss
:=
true
.
B
io
.
in
.
ready
:=
true
.
B
io
.
mem_acquire
.
valid
:=
pft
.
io
.
req
.
valid
io
.
mem_acquire
.
bits
.
cmd
:=
Mux
(
pft
.
io
.
req
.
bits
.
write
,
MemoryOpConstants
.
M_PFW
,
MemoryOpConstants
.
M_PFR
)
io
.
mem_acquire
.
bits
.
addr
:=
pft
.
io
.
req
.
bits
.
addr
io
.
mem_acquire
.
bits
.
id
:=
pft
.
io
.
req
.
bits
.
id
pft
.
io
.
req
.
ready
:=
io
.
mem_acquire
.
ready
val
mem_acquire_source
=
Wire
(
DecoupledIO
(
new
L1plusCacheReq
))
mem_acquire_source
.
valid
:=
pft
.
io
.
req
.
valid
mem_acquire_source
.
bits
.
cmd
:=
Mux
(
pft
.
io
.
req
.
bits
.
write
,
MemoryOpConstants
.
M_PFW
,
MemoryOpConstants
.
M_PFR
)
mem_acquire_source
.
bits
.
addr
:=
pft
.
io
.
req
.
bits
.
addr
mem_acquire_source
.
bits
.
id
:=
pft
.
io
.
req
.
bits
.
id
pft
.
io
.
req
.
ready
:=
mem_acquire_source
.
ready
latch_decoupled
(
mem_acquire_source
,
io
.
mem_acquire
)
pft
.
io
.
resp
.
valid
:=
io
.
mem_grant
.
valid
pft
.
io
.
resp
.
bits
.
id
:=
io
.
mem_grant
.
bits
.
id
(
streamParams
.
totalWidth
-
1
,
0
)
...
...
@@ -46,9 +65,10 @@ class L1plusPrefetcher extends PrefetchModule {
pft
.
io
.
finish
.
ready
:=
true
.
B
// debug info
XSDebug
(
p
"io.in: v=${io.in.valid} r=${io.in.ready} ${io.in.bits}\n"
)
XSDebug
(
p
"io.mem_acquire: v=${io.mem_acquire.valid} r=${io.mem_acquire.ready} ${io.mem_acquire.bits}\n"
)
XSDebug
(
p
"io.mem_grant: v=${io.mem_grant.valid} r=${io.mem_grant.ready} ${io.mem_grant.bits}\n"
)
XSDebug
(
p
"io.in: v=${io.in.valid} r=${io.in.ready} ${io.in.bits}\n"
)
XSDebug
(
p
"mem_acquire_source: v=${mem_acquire_source.valid} r=${mem_acquire_source.ready} ${mem_acquire_source.bits}"
)
XSDebug
(
p
"io.mem_acquire: v=${io.mem_acquire.valid} r=${io.mem_acquire.ready} ${io.mem_acquire.bits}\n"
)
XSDebug
(
p
"io.mem_grant: v=${io.mem_grant.valid} r=${io.mem_grant.ready} ${io.mem_grant.bits}\n"
)
if
(!
env
.
FPGAPlatform
&&
!
env
.
DualCore
)
{
ExcitingUtils
.
addSource
(
io
.
mem_acquire
.
fire
(),
"perfCntL1plusPrefetchReqCnt"
,
Perf
)
...
...
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