From 7157d58089bf54e8769b53e8fe3424bf7efd9431 Mon Sep 17 00:00:00 2001
From: zhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>
Date: Sat, 20 Feb 2021 18:57:45 +0800
Subject: [PATCH] L1plusPrefetcher: add latch of l1+prefetch req for timing
 optimization

---
 .../cache/prefetch/L1plusPrefetcher.scala     | 36 ++++++++++++++-----
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala b/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
index d7c94650a..99a4d2766 100644
--- a/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
+++ b/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala
@@ -24,6 +24,23 @@ class L1plusPrefetcher extends PrefetchModule {
     val mem_grant = Flipped(DecoupledIO(new L1plusCacheResp))
   })
 
+  def latch_decoupled[T <: Data](source: DecoupledIO[T], sink: DecoupledIO[T]) = {
+    val latch = Reg(source.bits.cloneType.asInstanceOf[T])
+    val valid = RegInit(false.B)
+    
+    when (sink.fire()) {
+      valid := false.B
+    }
+    when (source.fire()) {
+      valid := true.B
+      latch := source.bits
+    }
+
+    sink.valid := valid
+    sink.bits := latch
+    source.ready := !valid || sink.fire()
+  }
+
   if (l1plusPrefetcherParameters.enable && l1plusPrefetcherParameters._type == "stream") {
     val streamParams = l1plusPrefetcherParameters.streamParams
     val pft = Module(new StreamPrefetch(streamParams))
@@ -33,11 +50,13 @@ class L1plusPrefetcher extends PrefetchModule {
     pft.io.train.bits.miss := true.B
     io.in.ready := true.B
 
-    io.mem_acquire.valid := pft.io.req.valid
-    io.mem_acquire.bits.cmd := Mux(pft.io.req.bits.write, MemoryOpConstants.M_PFW, MemoryOpConstants.M_PFR)
-    io.mem_acquire.bits.addr := pft.io.req.bits.addr
-    io.mem_acquire.bits.id := pft.io.req.bits.id
-    pft.io.req.ready := io.mem_acquire.ready
+    val mem_acquire_source = Wire(DecoupledIO(new L1plusCacheReq))
+    mem_acquire_source.valid := pft.io.req.valid
+    mem_acquire_source.bits.cmd := Mux(pft.io.req.bits.write, MemoryOpConstants.M_PFW, MemoryOpConstants.M_PFR)
+    mem_acquire_source.bits.addr := pft.io.req.bits.addr
+    mem_acquire_source.bits.id := pft.io.req.bits.id
+    pft.io.req.ready := mem_acquire_source.ready
+    latch_decoupled(mem_acquire_source, io.mem_acquire)
 
     pft.io.resp.valid := io.mem_grant.valid
     pft.io.resp.bits.id := io.mem_grant.bits.id(streamParams.totalWidth - 1, 0)
@@ -46,9 +65,10 @@ class L1plusPrefetcher extends PrefetchModule {
     pft.io.finish.ready := true.B
 
     // debug info
-    XSDebug(p"io.in:          v=${io.in.valid} r=${io.in.ready} ${io.in.bits}\n")
-    XSDebug(p"io.mem_acquire: v=${io.mem_acquire.valid} r=${io.mem_acquire.ready} ${io.mem_acquire.bits}\n")
-    XSDebug(p"io.mem_grant:   v=${io.mem_grant.valid} r=${io.mem_grant.ready} ${io.mem_grant.bits}\n")
+    XSDebug(p"io.in:              v=${io.in.valid} r=${io.in.ready} ${io.in.bits}\n")
+    XSDebug(p"mem_acquire_source: v=${mem_acquire_source.valid} r=${mem_acquire_source.ready} ${mem_acquire_source.bits}")
+    XSDebug(p"io.mem_acquire:     v=${io.mem_acquire.valid} r=${io.mem_acquire.ready} ${io.mem_acquire.bits}\n")
+    XSDebug(p"io.mem_grant:       v=${io.mem_grant.valid} r=${io.mem_grant.ready} ${io.mem_grant.bits}\n")
 
     if (!env.FPGAPlatform && !env.DualCore) {
       ExcitingUtils.addSource(io.mem_acquire.fire(), "perfCntL1plusPrefetchReqCnt", Perf)
-- 
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