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体验新版 GitCode,发现更多精彩内容 >>
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6e4a4779
编写于
11月 17, 2022
作者:
C
czw
提交者:
ZhangZifei
1月 06, 2023
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电子邮件补丁
差异文件
refactor(ReservationStationStd): success for povray, mcf, gcc
TODO: modify the asynchronous read regfile to synchronous read regfile
上级
d7531d35
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
4 addition
and
10 deletion
+4
-10
src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
...cala/xiangshan/backend/issue/ReservationStationBase.scala
+2
-6
src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala
...scala/xiangshan/backend/issue/ReservationStationStd.scala
+2
-4
未找到文件。
src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
浏览文件 @
6e4a4779
...
@@ -504,7 +504,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -504,7 +504,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
// Do the read data arbitration
// Do the read data arbitration
val
s1_is_first_issue
=
Wire
(
Vec
(
params
.
numDeq
,
Bool
()))
val
s1_is_first_issue
=
Wire
(
Vec
(
params
.
numDeq
,
Bool
()))
val
s1_all_src_ready
=
Wire
(
Vec
(
params
.
numDeq
,
Bool
()))
val
s1_all_src_ready
=
Wire
(
Vec
(
params
.
numDeq
,
Bool
()))
val
s1_out_addr
=
Wire
(
Vec
(
params
.
numDeq
,
UInt
(
params
.
numEntries
.
W
)))
val
dataArrayWrite
=
Wire
(
Vec
(
params
.
numEnq
,
new
Bundle
{
val
dataArrayWrite
=
Wire
(
Vec
(
params
.
numEnq
,
new
Bundle
{
val
enable
=
Bool
()
val
enable
=
Bool
()
val
addr
=
UInt
(
params
.
numEntries
.
W
)
val
addr
=
UInt
(
params
.
numEntries
.
W
)
...
@@ -525,9 +524,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -525,9 +524,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
s1_out
(
i
).
bits
.
uop
:=
Mux
(
s1_issue_oldest
(
i
),
payloadArray
.
io
.
read
.
last
.
data
,
s1_out
(
i
).
bits
.
uop
:=
Mux
(
s1_issue_oldest
(
i
),
payloadArray
.
io
.
read
.
last
.
data
,
Mux
(
s1_in_selectPtrValid
(
i
),
payloadArray
.
io
.
read
(
i
).
data
,
s1_dispatchUops_dup
.
head
(
i
).
bits
))
Mux
(
s1_in_selectPtrValid
(
i
),
payloadArray
.
io
.
read
(
i
).
data
,
s1_dispatchUops_dup
.
head
(
i
).
bits
))
s1_out_addr
(
i
)
:=
Mux
(
s1_issue_oldest
(
i
),
s1_oldestSel
.
bits
,
Mux
(
s1_in_selectPtrValid
(
i
),
select
.
io
.
grant
(
i
).
bits
,
dataArrayWrite
(
i
).
addr
))
s1_is_first_issue
(
i
)
:=
Mux
(
s1_issue_oldest
(
i
),
statusArray
.
io
.
isFirstIssue
.
last
,
s1_is_first_issue
(
i
)
:=
Mux
(
s1_issue_oldest
(
i
),
statusArray
.
io
.
isFirstIssue
.
last
,
Mux
(
s1_in_selectPtrValid
(
i
),
statusArray
.
io
.
isFirstIssue
(
params
.
numEnq
+
i
),
Mux
(
s1_in_selectPtrValid
(
i
),
statusArray
.
io
.
isFirstIssue
(
params
.
numEnq
+
i
),
statusArray
.
io
.
update
(
i
).
data
.
isFirstIssue
))
statusArray
.
io
.
update
(
i
).
data
.
isFirstIssue
))
...
@@ -682,7 +678,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -682,7 +678,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
a
:=
b
a
:=
b
}
}
}
else
{
}
else
{
readData
:=
readIntRf_asyn
.
slice
(
i
*
numIntRfPorts
,(
i
+
1
)*
numIntRfPorts
).
map
(
_
.
data
)
readData
:=
DontCare
val
readAddr0
=
readIntRf_asyn
.
slice
(
i
*
numIntRfPorts
,(
i
+
1
)*
numIntRfPorts
).
map
(
_
.
addr
)
val
readAddr0
=
readIntRf_asyn
.
slice
(
i
*
numIntRfPorts
,(
i
+
1
)*
numIntRfPorts
).
map
(
_
.
addr
)
val
readAddr1
=
readFpRf_asyn
.
slice
(
i
*
numFpRfPorts
,(
i
+
1
)*
numFpRfPorts
).
map
(
_
.
addr
)
val
readAddr1
=
readFpRf_asyn
.
slice
(
i
*
numFpRfPorts
,(
i
+
1
)*
numFpRfPorts
).
map
(
_
.
addr
)
(
readAddr0
.
zip
(
readAddr1
)).
zip
(
readAddr
.
bits
.
uop
.
psrc
).
foreach
{
(
readAddr0
.
zip
(
readAddr1
)).
zip
(
readAddr
.
bits
.
uop
.
psrc
).
foreach
{
...
@@ -700,7 +696,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
...
@@ -700,7 +696,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
immExt
immExt
}
}
val
dataSlowCaptureAddr
=
s1_
out_addr
val
dataSlowCaptureAddr
=
s1_
issuePtrOH
.
map
(
_
.
bits
)
for
((
port
,
addr
)
<-
dataSelect
.
io
.
fromSlowPorts
.
zip
(
dataSlowCaptureAddr
))
{
for
((
port
,
addr
)
<-
dataSelect
.
io
.
fromSlowPorts
.
zip
(
dataSlowCaptureAddr
))
{
for
(
j
<-
0
until
params
.
numSrc
)
{
for
(
j
<-
0
until
params
.
numSrc
)
{
port
(
j
)
:=
VecInit
(
dataArrayMultiWrite
.
map
(
w
=>
w
.
enable
&&
(
addr
&
w
.
addr
(
j
)).
asUInt
.
orR
)).
asUInt
port
(
j
)
:=
VecInit
(
dataArrayMultiWrite
.
map
(
w
=>
w
.
enable
&&
(
addr
&
w
.
addr
(
j
)).
asUInt
.
orR
)).
asUInt
...
...
src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala
浏览文件 @
6e4a4779
...
@@ -35,9 +35,7 @@ class StdRSImp(params: RSParams, wrapper: StdRSWrapper) extends BaseReservationS
...
@@ -35,9 +35,7 @@ class StdRSImp(params: RSParams, wrapper: StdRSWrapper) extends BaseReservationS
class
StdRS
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
BaseReservationStation
(
params
)
class
StdRS
(
params
:
RSParams
)(
implicit
p
:
Parameters
)
extends
BaseReservationStation
(
params
)
with
RSDropNotOnRedirect
{
with
RSDropNotOnRedirect
{
for
(((
statusUpdate
,
uop
),
i
)
<-
statusArray
.
io
.
update
.
zip
(
s1_payloadUops
).
zipWithIndex
)
{
for
((
uop
,
i
)
<-
s1_payloadUops
.
zipWithIndex
)
{
when
(
uop
.
needRfRPort
(
0
,
true
,
false
))
{
s1_deqRfDataSel
(
i
)(
0
)
:=
Mux
(
uop
.
needRfRPort
(
0
,
true
,
true
),
readFpRf_asyn
(
i
).
data
,
readIntRf_asyn
(
i
).
data
)
s1_deqRfDataSel
(
i
)(
0
)
:=
enqReverse
(
readFpRf_asyn
)(
i
).
data
}
}
}
}
}
\ No newline at end of file
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