From 6e4a4779713ba19a596bc3de066af19a766813a1 Mon Sep 17 00:00:00 2001
From: czw <1753182770@qq.com>
Date: Thu, 17 Nov 2022 16:19:54 +0800
Subject: [PATCH] refactor(ReservationStationStd): success for povray, mcf, gcc

TODO: modify the asynchronous read regfile to synchronous read regfile
---
 .../xiangshan/backend/issue/ReservationStationBase.scala  | 8 ++------
 .../xiangshan/backend/issue/ReservationStationStd.scala   | 6 ++----
 2 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala b/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
index 3c3a5eb0a..516970a9e 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStationBase.scala
@@ -504,7 +504,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
   // Do the read data arbitration
   val s1_is_first_issue = Wire(Vec(params.numDeq, Bool()))
   val s1_all_src_ready = Wire(Vec(params.numDeq, Bool()))
-  val s1_out_addr = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
   val dataArrayWrite = Wire(Vec(params.numEnq, new Bundle{
     val enable = Bool()
     val addr   = UInt(params.numEntries.W)
@@ -525,9 +524,6 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
     s1_out(i).bits.uop := Mux(s1_issue_oldest(i), payloadArray.io.read.last.data,
       Mux(s1_in_selectPtrValid(i), payloadArray.io.read(i).data, s1_dispatchUops_dup.head(i).bits))
 
-    s1_out_addr(i) := Mux(s1_issue_oldest(i), s1_oldestSel.bits,
-      Mux(s1_in_selectPtrValid(i), select.io.grant(i).bits, dataArrayWrite(i).addr))
-
     s1_is_first_issue(i) := Mux(s1_issue_oldest(i), statusArray.io.isFirstIssue.last,
       Mux(s1_in_selectPtrValid(i), statusArray.io.isFirstIssue(params.numEnq + i),
         statusArray.io.update(i).data.isFirstIssue))
@@ -682,7 +678,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
           a := b
       }
     }else{
-      readData := readIntRf_asyn.slice(i*numIntRfPorts,(i+1)*numIntRfPorts).map(_.data)
+      readData := DontCare
       val readAddr0 = readIntRf_asyn.slice(i*numIntRfPorts,(i+1)*numIntRfPorts).map(_.addr)
       val readAddr1 = readFpRf_asyn.slice(i*numFpRfPorts,(i+1)*numFpRfPorts).map(_.addr)
       (readAddr0.zip(readAddr1)).zip(readAddr.bits.uop.psrc).foreach{
@@ -700,7 +696,7 @@ class BaseReservationStation(params: RSParams)(implicit p: Parameters) extends R
     immExt
   }
 
-  val dataSlowCaptureAddr = s1_out_addr
+  val dataSlowCaptureAddr = s1_issuePtrOH.map(_.bits)
   for ((port, addr) <- dataSelect.io.fromSlowPorts.zip(dataSlowCaptureAddr)) {
     for (j <- 0 until params.numSrc) {
       port(j) := VecInit(dataArrayMultiWrite.map(w => w.enable && (addr & w.addr(j)).asUInt.orR)).asUInt
diff --git a/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala b/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala
index a01a2caf4..bb2a7cbf7 100644
--- a/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStationStd.scala
@@ -35,9 +35,7 @@ class StdRSImp(params: RSParams, wrapper: StdRSWrapper) extends BaseReservationS
 
 class StdRS(params: RSParams)(implicit p: Parameters) extends BaseReservationStation(params)
   with RSDropNotOnRedirect {
-  for (((statusUpdate, uop), i) <- statusArray.io.update.zip(s1_payloadUops).zipWithIndex) {
-    when (uop.needRfRPort(0, true, false)) {
-      s1_deqRfDataSel(i)(0) := enqReverse(readFpRf_asyn)(i).data
-    }
+  for ((uop, i) <- s1_payloadUops.zipWithIndex) {
+    s1_deqRfDataSel(i)(0) := Mux(uop.needRfRPort(0, true, true), readFpRf_asyn(i).data, readIntRf_asyn(i).data)
   }
 }
\ No newline at end of file
-- 
GitLab