Backend: change dispatch2->dispatch

IssueQueue: delete io.enq.redirect

src/main/scala/xiangshan/backend/Backend.scala

@@ -55,8 +55,8 @@ class Backend(implicit val p: XSConfig) extends XSModule
     assert(!(needBypass(eu) && !needWakeup(eu))) // needBypass but dont needWakeup is not allowed
     val iq = Module(new IssueQueue(eu.fuTypeInt, wakeupCnt, bypassCnt, eu.fixedDelay))
     iq.io.redirect <> redirect
-    iq.io.enqCtrl <> dispatch2.io.enqIQCtrl(i)
-    iq.io.enqData <> dispatch2.io.enqIQData(i)
+    iq.io.enqCtrl <> dispatch.io.enqIQCtrl(i)
+    iq.io.enqData <> dispatch.io.enqIQData(i)
     val wuUnitsOut = exeUnits.filter(e => needWakeup(e)).map(_.io.out)
     for(i <- iq.io.wakeUpPorts.indices) {
       iq.io.wakeUpPorts(i).bits <> wuUnitsOut(i).bits

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -309,9 +309,6 @@ class IssueQueue(val fuTypeInt: BigInt, val wakeupCnt: Int, val bypassCnt: Int =
   io.deq.bits.uop.freelistAllocPtr := freelistAllocPtr(dequeueSelect)
   io.deq.bits.uop.roqIdx := roqIdx(dequeueSelect)
 
-  //TODO
-  io.deq.bits.redirect := DontCare
-
   io.deq.bits.src1 := src1Data(dequeueSelect)
   io.deq.bits.src2 := src2Data(dequeueSelect)
   io.deq.bits.src3 := src3Data(dequeueSelect)