@@ -14,6 +14,20 @@ Copyright 2020-2022 by Peng Cheng Laboratory.
* Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io
## Publications
### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors.
It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc.
This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).
@@ -119,13 +133,3 @@ In the development of XiangShan, some sub-modules from the open-source community
| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).
## Publications
### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors.
It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc.
This paper is awarded all three available badges for artifacts evaluation.
