From 5986560e7df8e49aeb0d9ca3630b53d96720b102 Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Sat, 24 Sep 2022 09:57:12 +0800 Subject: [PATCH] Update Artifact Evaluation badges to README.md (#1789) * Update Artifact Evaluation badges to README.md --- README.md | 24 ++++++++++++++---------- readme.zh-cn.md | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/README.md b/README.md index 07b7b5a2f..2a37b2b75 100644 --- a/README.md +++ b/README.md @@ -14,6 +14,20 @@ Copyright 2020-2022 by Peng Cheng Laboratory. * Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io +## Publications + +### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology + +Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. +It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. +This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced). + +![Artifacts Available](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/artifacts_available_dl.jpg) +![Artifacts Evaluated — Functional](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/artifacts_evaluated_functional_dl.jpg) +![Results Reproduced](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/results_reproduced_dl.jpg) + +[Paper PDF](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/publications/micro2022-xiangshan.pdf) | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD) + ## Follow us Wechat/微信：香山开源处理器 @@ -119,13 +133,3 @@ In the development of XiangShan, some sub-modules from the open-source community | Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. | We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE). - -## Publications - -### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology - -Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. -It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. -This paper is awarded all three available badges for artifacts evaluation. - -[Paper PDF](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/publications/micro2022-xiangshan.pdf) | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD) diff --git a/readme.zh-cn.md b/readme.zh-cn.md index 9cc7ce9e4..205bbc78a 100644 --- a/readme.zh-cn.md +++ b/readme.zh-cn.md @@ -14,6 +14,20 @@ English Readme is [here](README.md). * 香山微结构文档已经发布，欢迎访问 https://xiangshan-doc.readthedocs.io + +## 论文发表情况 + +### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology + +我们在 MICRO'22 会议上的论文介绍了香山处理器及敏捷开发实践经验，包括一些面向设计、功能验证、调试、性能评估等方面的敏捷开发工具。论文得到了 Artifact Evaluation 的所有三个徽章。 + +![Artifacts Available](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/artifacts_available_dl.jpg) +![Artifacts Evaluated — Functional](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/artifacts_evaluated_functional_dl.jpg) +![Results Reproduced](https://github.com/OpenXiangShan/XiangShan-doc/raw/main/publications/images/results_reproduced_dl.jpg) + +[Paper PDF](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/publications/micro2022-xiangshan.pdf) | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD) + + ## 关注我们 Wechat/微信：香山开源处理器 @@ -114,11 +128,3 @@ make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10 | Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip) | 我们复用了来自 rocket-chip 的 Diplomacy 框架和 Tilelink 工具，来协商总线. | 我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。 - -## 论文发表情况 - -### MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology - -我们在 MICRO'22 会议上的论文介绍了香山处理器及敏捷开发实践经验，包括一些面向设计、功能验证、调试、性能评估等方面的敏捷开发工具。论文得到了 Aritifact Evaluation 的所有三个徽章。 - -[Paper PDF](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/publications/micro2022-xiangshan.pdf) | IEEE Xplore (TBD) | ACM DL (TBD) | BibTeX (TBD) -- GitLab