fakeICache: fetch instructions 2-bytes aligned

decoder: fix bug in immrvc

dummy passes!

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 import xiangshan._
-import utils.{LookupTree, SignExt, ZeroExt}
+import utils._
 import xiangshan.backend._
 import xiangshan.backend.decode.isa.RVCInstr
 import xiangshan.{CfCtrl, CtrlFlow}
@@ -99,7 +99,7 @@ class Decoder extends XSModule with HasInstrType {
     InstrU  -> SignExt(Cat(instr(31, 12), 0.U(12.W)), XLEN),//fixed
     InstrJ  -> SignExt(Cat(instr(31), instr(19, 12), instr(20), instr(30, 21), 0.U(1.W)), XLEN)
   ))
-  val immrvc = LookupTree(instrType, List(
+  val immrvc = LookupTree(rvcImmType, List(
     RVCInstr.ImmNone  -> 0.U(XLEN.W),
     RVCInstr.ImmLWSP  -> ZeroExt(Cat(instr(3,2), instr(12), instr(6,4), 0.U(2.W)), XLEN),
     RVCInstr.ImmLDSP  -> ZeroExt(Cat(instr(4,2), instr(12), instr(6,5), 0.U(3.W)), XLEN),
@@ -144,4 +144,12 @@ class Decoder extends XSModule with HasInstrType {
     io.out.ctrl.lsrc1 := 10.U // a0
   }
   io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr
+
+  XSDebug("in:  instr=%x pc=%x excepVec=%b intrVec=%b crossPageIPFFix=%d\n",
+    io.in.instr, io.in.pc, io.in.exceptionVec.asUInt, io.in.intrVec.asUInt, io.in.crossPageIPFFix)
+  XSDebug("out: src1Type=%b src2Type=%b src3Type=%b lsrc1=%d lsrc2=%d lsrc3=%d ldest=%d fuType=%b fuOpType=%b\n",
+    io.out.ctrl.src1Type, io.out.ctrl.src2Type, io.out.ctrl.src3Type, io.out.ctrl.lsrc1, io.out.ctrl.lsrc2, io.out.ctrl.lsrc3, io.out.ctrl.ldest, io.out.ctrl.fuType, io.out.ctrl.fuOpType)
+  XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d isRVF=%d imm=%x\n",
+    io.out.ctrl.rfWen, io.out.ctrl.fpWen, io.out.ctrl.isXSTrap, io.out.ctrl.noSpecExec, io.out.ctrl.isBlocked, io.out.ctrl.isRVF, io.out.ctrl.imm)
+
 }

src/main/scala/xiangshan/frontend/FakeICache.scala

@@ -81,31 +81,31 @@ class FakeCache extends XSModule with HasICacheConst {
   def index(addr: UInt): UInt = ((addr & offsetMask.U) >> log2Ceil(DataBytes)).asUInt()
   def inRange(idx: UInt): Bool = idx < (memByte / 8).U
 
-  val ramOut = Wire(Vec(FetchWidth,UInt(32.W)))
+  // val ramOut = Wire(Vec(FetchWidth,UInt(32.W)))
   for(i <- ramHelpers.indices) {
     val rIdx = index(gpc) + i.U
     ramHelpers(i).rIdx := rIdx
-    when(gpc(2) === "b0".U){
-      //little ending
-      ramOut(0) := ramHelpers(0).rdata.tail(32)
-      ramOut(1) := ramHelpers(0).rdata.head(32)
-      ramOut(2) := ramHelpers(1).rdata.tail(32)
-      ramOut(3) := ramHelpers(1).rdata.head(32)
-      ramOut(4) := ramHelpers(2).rdata.tail(32)
-      ramOut(5) := ramHelpers(2).rdata.head(32)
-      ramOut(6) := ramHelpers(3).rdata.tail(32)
-      ramOut(7) := ramHelpers(3).rdata.head(32)
-    } .otherwise {
-      ramOut(0) := ramHelpers(0).rdata.head(32)
-      ramOut(1) := ramHelpers(1).rdata.tail(32)
-      ramOut(2) := ramHelpers(1).rdata.head(32)
-      ramOut(3) := ramHelpers(2).rdata.tail(32)
-      ramOut(4) := ramHelpers(2).rdata.head(32)
-      ramOut(5) := ramHelpers(3).rdata.tail(32)
-      ramOut(6) := ramHelpers(3).rdata.head(32)
-      ramOut(7) := ramHelpers(4).rdata.tail(32)
-
-    }
+    // when(gpc(2) === "b0".U){
+    //   //little ending
+    //   ramOut(0) := ramHelpers(0).rdata.tail(32)
+    //   ramOut(1) := ramHelpers(0).rdata.head(32)
+    //   ramOut(2) := ramHelpers(1).rdata.tail(32)
+    //   ramOut(3) := ramHelpers(1).rdata.head(32)
+    //   ramOut(4) := ramHelpers(2).rdata.tail(32)
+    //   ramOut(5) := ramHelpers(2).rdata.head(32)
+    //   ramOut(6) := ramHelpers(3).rdata.tail(32)
+    //   ramOut(7) := ramHelpers(3).rdata.head(32)
+    // } .otherwise {
+    //   ramOut(0) := ramHelpers(0).rdata.head(32)
+    //   ramOut(1) := ramHelpers(1).rdata.tail(32)
+    //   ramOut(2) := ramHelpers(1).rdata.head(32)
+    //   ramOut(3) := ramHelpers(2).rdata.tail(32)
+    //   ramOut(4) := ramHelpers(2).rdata.head(32)
+    //   ramOut(5) := ramHelpers(3).rdata.tail(32)
+    //   ramOut(6) := ramHelpers(3).rdata.head(32)
+    //   ramOut(7) := ramHelpers(4).rdata.tail(32)
+
+    // }
     Seq(
       ramHelpers(i).wmask,
       ramHelpers(i).wdata,
@@ -114,17 +114,21 @@ class FakeCache extends XSModule with HasICacheConst {
     ).foreach(_ := 0.U)
   }
 
+  val ramOut = Wire(UInt((XLEN * 5).W))
+  ramOut := Cat(ramHelpers(4).rdata, ramHelpers(3).rdata, ramHelpers(2).rdata, ramHelpers(1).rdata, ramHelpers(0).rdata) >> (gpc(2,1) << 4)
+
+
   XSDebug("[ICache-Stage1] s1_valid:%d || s2_ready:%d || s1_pc:%x",s1_valid,s2_ready,gpc)
   XSDebug(false,s1_fire,"------> s1 fire!!!")
   XSDebug(false,true.B,"\n")
 
-  XSDebug("[Stage1_data] instr1:0x%x   instr2:0x%x\n",ramOut(0).asUInt,ramOut(1).asUInt)
+  // XSDebug("[Stage1_data] instr1:0x%x   instr2:0x%x\n",ramOut(0).asUInt,ramOut(1).asUInt)
 
   //----------------
   //  ICache Stage2
   //----------------
   val s2_valid = RegEnable(next=s1_valid,init=false.B,enable=s1_fire)
-  val s2_ram_out = RegEnable(next=ramOut,enable=s1_fire)
+  val s2_ram_out = RegEnable(next=ramOut(XLEN * 4 - 1, 0),enable=s1_fire)
   val s2_pc = RegEnable(next = gpc, enable = s1_fire)
   val s3_ready = WireInit(false.B)
   val s2_fire  = s2_valid && s3_ready
@@ -134,7 +138,7 @@ class FakeCache extends XSModule with HasICacheConst {
   XSDebug(false,s2_fire,"------> s2 fire!!!")
   XSDebug(false,true.B,"\n")
 
-  XSDebug("[Stage2_data] instr1:0x%x   instr2:0x%x\n",s2_ram_out(0).asUInt,s2_ram_out(1).asUInt)
+  // XSDebug("[Stage2_data] instr1:0x%x   instr2:0x%x\n",s2_ram_out(0).asUInt,s2_ram_out(1).asUInt)
   //----------------
   //  ICache Stage3
   //----------------
@@ -147,7 +151,7 @@ class FakeCache extends XSModule with HasICacheConst {
   XSDebug("[ICache-Stage3] s3_valid:%d || s3_ready:%d ",s3_valid,s3_ready)
   XSDebug(false,true.B,"\n")
 
-  XSDebug("[Stage3_data] instr1:0x%x   instr2:0x%x\n",s3_ram_out(0).asUInt,s3_ram_out(1).asUInt)
+  // XSDebug("[Stage3_data] instr1:0x%x   instr2:0x%x\n",s3_ram_out(0).asUInt,s3_ram_out(1).asUInt)
   XSDebug("[Flush icache] flush:%b\n", io.flush)
 
   // when(needflush){
@@ -162,6 +166,6 @@ class FakeCache extends XSModule with HasICacheConst {
 
   io.out.valid := s3_valid
   io.out.bits.pc := s3_pc
-  io.out.bits.data := s3_ram_out.asUInt
+  io.out.bits.data := s3_ram_out
   io.out.bits.mask := mask(s3_pc)
 }
\ No newline at end of file