Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
4ed69b39
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
12 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
4ed69b39
编写于
8月 06, 2020
作者:
Z
zhanglinjuan
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
fakeICache: fetch instructions 2-bytes aligned
decoder: fix bug in immrvc dummy passes!
上级
a1a4424b
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
41 addition
and
29 deletion
+41
-29
src/main/scala/xiangshan/backend/decode/Decoder.scala
src/main/scala/xiangshan/backend/decode/Decoder.scala
+10
-2
src/main/scala/xiangshan/frontend/FakeICache.scala
src/main/scala/xiangshan/frontend/FakeICache.scala
+31
-27
未找到文件。
src/main/scala/xiangshan/backend/decode/Decoder.scala
浏览文件 @
4ed69b39
...
...
@@ -4,7 +4,7 @@ import chisel3._
import
chisel3.util._
import
chisel3.util.experimental.BoringUtils
import
xiangshan._
import
utils.
{
LookupTree
,
SignExt
,
ZeroExt
}
import
utils.
_
import
xiangshan.backend._
import
xiangshan.backend.decode.isa.RVCInstr
import
xiangshan.
{
CfCtrl
,
CtrlFlow
}
...
...
@@ -99,7 +99,7 @@ class Decoder extends XSModule with HasInstrType {
InstrU
->
SignExt
(
Cat
(
instr
(
31
,
12
),
0.
U
(
12.
W
)),
XLEN
),
//fixed
InstrJ
->
SignExt
(
Cat
(
instr
(
31
),
instr
(
19
,
12
),
instr
(
20
),
instr
(
30
,
21
),
0.
U
(
1.
W
)),
XLEN
)
))
val
immrvc
=
LookupTree
(
instr
Type
,
List
(
val
immrvc
=
LookupTree
(
rvcImm
Type
,
List
(
RVCInstr
.
ImmNone
->
0.
U
(
XLEN
.
W
),
RVCInstr
.
ImmLWSP
->
ZeroExt
(
Cat
(
instr
(
3
,
2
),
instr
(
12
),
instr
(
6
,
4
),
0.
U
(
2.
W
)),
XLEN
),
RVCInstr
.
ImmLDSP
->
ZeroExt
(
Cat
(
instr
(
4
,
2
),
instr
(
12
),
instr
(
6
,
5
),
0.
U
(
3.
W
)),
XLEN
),
...
...
@@ -144,4 +144,12 @@ class Decoder extends XSModule with HasInstrType {
io
.
out
.
ctrl
.
lsrc1
:=
10.
U
// a0
}
io
.
out
.
ctrl
.
noSpecExec
:=
io
.
out
.
ctrl
.
isXSTrap
||
io
.
out
.
ctrl
.
fuType
===
FuType
.
csr
XSDebug
(
"in: instr=%x pc=%x excepVec=%b intrVec=%b crossPageIPFFix=%d\n"
,
io
.
in
.
instr
,
io
.
in
.
pc
,
io
.
in
.
exceptionVec
.
asUInt
,
io
.
in
.
intrVec
.
asUInt
,
io
.
in
.
crossPageIPFFix
)
XSDebug
(
"out: src1Type=%b src2Type=%b src3Type=%b lsrc1=%d lsrc2=%d lsrc3=%d ldest=%d fuType=%b fuOpType=%b\n"
,
io
.
out
.
ctrl
.
src1Type
,
io
.
out
.
ctrl
.
src2Type
,
io
.
out
.
ctrl
.
src3Type
,
io
.
out
.
ctrl
.
lsrc1
,
io
.
out
.
ctrl
.
lsrc2
,
io
.
out
.
ctrl
.
lsrc3
,
io
.
out
.
ctrl
.
ldest
,
io
.
out
.
ctrl
.
fuType
,
io
.
out
.
ctrl
.
fuOpType
)
XSDebug
(
"out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d isRVF=%d imm=%x\n"
,
io
.
out
.
ctrl
.
rfWen
,
io
.
out
.
ctrl
.
fpWen
,
io
.
out
.
ctrl
.
isXSTrap
,
io
.
out
.
ctrl
.
noSpecExec
,
io
.
out
.
ctrl
.
isBlocked
,
io
.
out
.
ctrl
.
isRVF
,
io
.
out
.
ctrl
.
imm
)
}
src/main/scala/xiangshan/frontend/FakeICache.scala
浏览文件 @
4ed69b39
...
...
@@ -81,31 +81,31 @@ class FakeCache extends XSModule with HasICacheConst {
def
index
(
addr
:
UInt
)
:
UInt
=
((
addr
&
offsetMask
.
U
)
>>
log2Ceil
(
DataBytes
)).
asUInt
()
def
inRange
(
idx
:
UInt
)
:
Bool
=
idx
<
(
memByte
/
8
).
U
val
ramOut
=
Wire
(
Vec
(
FetchWidth
,
UInt
(
32.
W
)))
//
val ramOut = Wire(Vec(FetchWidth,UInt(32.W)))
for
(
i
<-
ramHelpers
.
indices
)
{
val
rIdx
=
index
(
gpc
)
+
i
.
U
ramHelpers
(
i
).
rIdx
:=
rIdx
when
(
gpc
(
2
)
===
"b0"
.
U
){
//little ending
ramOut
(
0
)
:=
ramHelpers
(
0
).
rdata
.
tail
(
32
)
ramOut
(
1
)
:=
ramHelpers
(
0
).
rdata
.
head
(
32
)
ramOut
(
2
)
:=
ramHelpers
(
1
).
rdata
.
tail
(
32
)
ramOut
(
3
)
:=
ramHelpers
(
1
).
rdata
.
head
(
32
)
ramOut
(
4
)
:=
ramHelpers
(
2
).
rdata
.
tail
(
32
)
ramOut
(
5
)
:=
ramHelpers
(
2
).
rdata
.
head
(
32
)
ramOut
(
6
)
:=
ramHelpers
(
3
).
rdata
.
tail
(
32
)
ramOut
(
7
)
:=
ramHelpers
(
3
).
rdata
.
head
(
32
)
}
.
otherwise
{
ramOut
(
0
)
:=
ramHelpers
(
0
).
rdata
.
head
(
32
)
ramOut
(
1
)
:=
ramHelpers
(
1
).
rdata
.
tail
(
32
)
ramOut
(
2
)
:=
ramHelpers
(
1
).
rdata
.
head
(
32
)
ramOut
(
3
)
:=
ramHelpers
(
2
).
rdata
.
tail
(
32
)
ramOut
(
4
)
:=
ramHelpers
(
2
).
rdata
.
head
(
32
)
ramOut
(
5
)
:=
ramHelpers
(
3
).
rdata
.
tail
(
32
)
ramOut
(
6
)
:=
ramHelpers
(
3
).
rdata
.
head
(
32
)
ramOut
(
7
)
:=
ramHelpers
(
4
).
rdata
.
tail
(
32
)
}
//
when(gpc(2) === "b0".U){
//
//little ending
//
ramOut(0) := ramHelpers(0).rdata.tail(32)
//
ramOut(1) := ramHelpers(0).rdata.head(32)
//
ramOut(2) := ramHelpers(1).rdata.tail(32)
//
ramOut(3) := ramHelpers(1).rdata.head(32)
//
ramOut(4) := ramHelpers(2).rdata.tail(32)
//
ramOut(5) := ramHelpers(2).rdata.head(32)
//
ramOut(6) := ramHelpers(3).rdata.tail(32)
//
ramOut(7) := ramHelpers(3).rdata.head(32)
//
} .otherwise {
//
ramOut(0) := ramHelpers(0).rdata.head(32)
//
ramOut(1) := ramHelpers(1).rdata.tail(32)
//
ramOut(2) := ramHelpers(1).rdata.head(32)
//
ramOut(3) := ramHelpers(2).rdata.tail(32)
//
ramOut(4) := ramHelpers(2).rdata.head(32)
//
ramOut(5) := ramHelpers(3).rdata.tail(32)
//
ramOut(6) := ramHelpers(3).rdata.head(32)
//
ramOut(7) := ramHelpers(4).rdata.tail(32)
//
}
Seq
(
ramHelpers
(
i
).
wmask
,
ramHelpers
(
i
).
wdata
,
...
...
@@ -114,17 +114,21 @@ class FakeCache extends XSModule with HasICacheConst {
).
foreach
(
_
:=
0.
U
)
}
val
ramOut
=
Wire
(
UInt
((
XLEN
*
5
).
W
))
ramOut
:=
Cat
(
ramHelpers
(
4
).
rdata
,
ramHelpers
(
3
).
rdata
,
ramHelpers
(
2
).
rdata
,
ramHelpers
(
1
).
rdata
,
ramHelpers
(
0
).
rdata
)
>>
(
gpc
(
2
,
1
)
<<
4
)
XSDebug
(
"[ICache-Stage1] s1_valid:%d || s2_ready:%d || s1_pc:%x"
,
s1_valid
,
s2_ready
,
gpc
)
XSDebug
(
false
,
s1_fire
,
"------> s1 fire!!!"
)
XSDebug
(
false
,
true
.
B
,
"\n"
)
XSDebug
(
"[Stage1_data] instr1:0x%x instr2:0x%x\n"
,
ramOut
(
0
).
asUInt
,
ramOut
(
1
).
asUInt
)
//
XSDebug("[Stage1_data] instr1:0x%x instr2:0x%x\n",ramOut(0).asUInt,ramOut(1).asUInt)
//----------------
// ICache Stage2
//----------------
val
s2_valid
=
RegEnable
(
next
=
s1_valid
,
init
=
false
.
B
,
enable
=
s1_fire
)
val
s2_ram_out
=
RegEnable
(
next
=
ramOut
,
enable
=
s1_fire
)
val
s2_ram_out
=
RegEnable
(
next
=
ramOut
(
XLEN
*
4
-
1
,
0
)
,
enable
=
s1_fire
)
val
s2_pc
=
RegEnable
(
next
=
gpc
,
enable
=
s1_fire
)
val
s3_ready
=
WireInit
(
false
.
B
)
val
s2_fire
=
s2_valid
&&
s3_ready
...
...
@@ -134,7 +138,7 @@ class FakeCache extends XSModule with HasICacheConst {
XSDebug
(
false
,
s2_fire
,
"------> s2 fire!!!"
)
XSDebug
(
false
,
true
.
B
,
"\n"
)
XSDebug
(
"[Stage2_data] instr1:0x%x instr2:0x%x\n"
,
s2_ram_out
(
0
).
asUInt
,
s2_ram_out
(
1
).
asUInt
)
//
XSDebug("[Stage2_data] instr1:0x%x instr2:0x%x\n",s2_ram_out(0).asUInt,s2_ram_out(1).asUInt)
//----------------
// ICache Stage3
//----------------
...
...
@@ -147,7 +151,7 @@ class FakeCache extends XSModule with HasICacheConst {
XSDebug
(
"[ICache-Stage3] s3_valid:%d || s3_ready:%d "
,
s3_valid
,
s3_ready
)
XSDebug
(
false
,
true
.
B
,
"\n"
)
XSDebug
(
"[Stage3_data] instr1:0x%x instr2:0x%x\n"
,
s3_ram_out
(
0
).
asUInt
,
s3_ram_out
(
1
).
asUInt
)
//
XSDebug("[Stage3_data] instr1:0x%x instr2:0x%x\n",s3_ram_out(0).asUInt,s3_ram_out(1).asUInt)
XSDebug
(
"[Flush icache] flush:%b\n"
,
io
.
flush
)
// when(needflush){
...
...
@@ -162,6 +166,6 @@ class FakeCache extends XSModule with HasICacheConst {
io
.
out
.
valid
:=
s3_valid
io
.
out
.
bits
.
pc
:=
s3_pc
io
.
out
.
bits
.
data
:=
s3_ram_out
.
asUInt
io
.
out
.
bits
.
data
:=
s3_ram_out
io
.
out
.
bits
.
mask
:=
mask
(
s3_pc
)
}
\ No newline at end of file
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录