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体验新版 GitCode,发现更多精彩内容 >>
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4a99cefe
编写于
11月 06, 2020
作者:
J
jinyue110
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差异文件
Merge branch 'icache-Non-Blocking' into icache-l1plus
上级
e3bbb124
043203e7
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
6 addition
and
6 deletion
+6
-6
debug/Makefile
debug/Makefile
+1
-2
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+3
-2
src/main/scala/xiangshan/cache/icacheMissQueue.scala
src/main/scala/xiangshan/cache/icacheMissQueue.scala
+2
-2
未找到文件。
debug/Makefile
浏览文件 @
4a99cefe
...
@@ -18,8 +18,7 @@ cache:
...
@@ -18,8 +18,7 @@ cache:
#2>&1 | tee > loader.log
#2>&1 | tee > loader.log
cpu
:
cpu
:
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
ALL
=
dummy
$(EMU_ARGS)
run
$(MAKE)
-C
$(AM_HOME)
/tests/cputest
$(ARCH)
ALL
=
hello-str
$(EMU_ARGS)
run 2>&1 |
tee
>
hello.log
#2>&1 | tee > dummy.log
# ------------------------------------------------------------------
# ------------------------------------------------------------------
# run different test sets
# run different test sets
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
4a99cefe
...
@@ -361,14 +361,15 @@ class ICache extends ICacheModule
...
@@ -361,14 +361,15 @@ class ICache extends ICacheModule
val
icacheMissQueue
=
Module
(
new
IcacheMissQueue
)
val
icacheMissQueue
=
Module
(
new
IcacheMissQueue
)
val
blocking
=
RegInit
(
false
.
B
)
val
blocking
=
RegInit
(
false
.
B
)
val
isICacheResp
=
icacheMissQueue
.
io
.
resp
.
valid
&&
icacheMissQueue
.
io
.
resp
.
bits
.
clientID
===
cacheID
.
U
(
2.
W
)
val
isICacheResp
=
icacheMissQueue
.
io
.
resp
.
valid
&&
icacheMissQueue
.
io
.
resp
.
bits
.
clientID
===
cacheID
.
U
(
2.
W
)
icacheMissQueue
.
io
.
req
.
valid
:=
s3_miss
&&
(
io
.
flush
===
0.
U
)
&&
!
blocking
//TODO: specificate flush condition
icacheMissQueue
.
io
.
req
.
valid
:=
s3_miss
&&
!
io
.
flush
(
1
)
&&
!
blocking
//TODO: specificate flush condition
icacheMissQueue
.
io
.
req
.
bits
.
apply
(
missAddr
=
groupPC
(
s3_tlb_resp
.
paddr
),
missIdx
=
s3_idx
,
missWaymask
=
s3_wayMask
,
source
=
cacheID
.
U
(
2.
W
))
icacheMissQueue
.
io
.
req
.
bits
.
apply
(
missAddr
=
groupPC
(
s3_tlb_resp
.
paddr
),
missIdx
=
s3_idx
,
missWaymask
=
s3_wayMask
,
source
=
cacheID
.
U
(
2.
W
))
icacheMissQueue
.
io
.
resp
.
ready
:=
io
.
resp
.
ready
icacheMissQueue
.
io
.
resp
.
ready
:=
io
.
resp
.
ready
icacheMissQueue
.
io
.
flush
:=
io
.
flush
(
1
)
icacheMissQueue
.
io
.
flush
:=
io
.
flush
(
1
)
when
(
icacheMissQueue
.
io
.
req
.
fire
()){
blocking
:=
true
.
B
}
when
(
icacheMissQueue
.
io
.
req
.
fire
()){
blocking
:=
true
.
B
}
.
elsewhen
(
icacheMissQueue
.
io
.
resp
.
fire
()
&&
isICacheResp
){
blocking
:=
false
.
B
}
.
elsewhen
(
blocking
&&
((
icacheMissQueue
.
io
.
resp
.
fire
()
&&
isICacheResp
)
||
io
.
flush
(
1
))
){
blocking
:=
false
.
B
}
XSDebug
(
blocking
&&
io
.
flush
(
1
),
"check for icache non-blocking"
)
//cache flush register
//cache flush register
val
icacheFlush
=
WireInit
(
false
.
B
)
val
icacheFlush
=
WireInit
(
false
.
B
)
val
cacheflushed
=
RegInit
(
false
.
B
)
val
cacheflushed
=
RegInit
(
false
.
B
)
...
...
src/main/scala/xiangshan/cache/icacheMissQueue.scala
浏览文件 @
4a99cefe
...
@@ -102,7 +102,6 @@ class IcacheMissEntry extends ICacheMissQueueModule
...
@@ -102,7 +102,6 @@ class IcacheMissEntry extends ICacheMissQueueModule
io
.
req
.
ready
:=
state
===
s_idle
io
.
req
.
ready
:=
state
===
s_idle
io
.
mem_acquire
.
valid
:=
state
===
s_memReadReq
io
.
mem_acquire
.
valid
:=
state
===
s_memReadReq
io
.
resp
.
valid
:=
state
===
s_wait_resp
//flush register
//flush register
val
needFlush
=
RegInit
(
false
.
B
)
val
needFlush
=
RegInit
(
false
.
B
)
...
@@ -162,7 +161,8 @@ class IcacheMissEntry extends ICacheMissQueueModule
...
@@ -162,7 +161,8 @@ class IcacheMissEntry extends ICacheMissQueueModule
io
.
mem_acquire
.
bits
.
addr
:=
req
.
addr
io
.
mem_acquire
.
bits
.
addr
:=
req
.
addr
io
.
mem_acquire
.
bits
.
id
:=
io
.
id
io
.
mem_acquire
.
bits
.
id
:=
io
.
id
//resp to icache
io
.
resp
.
valid
:=
(
state
===
s_wait_resp
)
&&
!
needFlush
XSDebug
(
"[ICache MSHR %d] (req)valid:%d ready:%d req.addr:%x waymask:%b || Register: req:%x \n"
,
io
.
id
.
asUInt
,
io
.
req
.
valid
,
io
.
req
.
ready
,
io
.
req
.
bits
.
addr
,
io
.
req
.
bits
.
waymask
,
req
.
asUInt
)
XSDebug
(
"[ICache MSHR %d] (req)valid:%d ready:%d req.addr:%x waymask:%b || Register: req:%x \n"
,
io
.
id
.
asUInt
,
io
.
req
.
valid
,
io
.
req
.
ready
,
io
.
req
.
bits
.
addr
,
io
.
req
.
bits
.
waymask
,
req
.
asUInt
)
XSDebug
(
"[ICache MSHR %d] (Info)state:%d needFlush:%d\n"
,
io
.
id
.
asUInt
,
state
,
needFlush
)
XSDebug
(
"[ICache MSHR %d] (Info)state:%d needFlush:%d\n"
,
io
.
id
.
asUInt
,
state
,
needFlush
)
...
...
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