Merge branch 'icache-Non-Blocking' into icache-l1plus

debug/Makefile

@@ -18,8 +18,7 @@ cache:
 	#2>&1 | tee > loader.log
 
 cpu:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=dummy $(EMU_ARGS) run
-	#2>&1 | tee > dummy.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) ALL=hello-str $(EMU_ARGS) run 2>&1 | tee > hello.log
 
 # ------------------------------------------------------------------
 # run different test sets

src/main/scala/xiangshan/cache/icache.scala

@@ -361,14 +361,15 @@ class ICache extends ICacheModule
   val icacheMissQueue = Module(new IcacheMissQueue)
   val blocking = RegInit(false.B)
   val isICacheResp = icacheMissQueue.io.resp.valid && icacheMissQueue.io.resp.bits.clientID === cacheID.U(2.W)
-  icacheMissQueue.io.req.valid := s3_miss && (io.flush === 0.U) && !blocking//TODO: specificate flush condition
+  icacheMissQueue.io.req.valid := s3_miss && !io.flush(1) && !blocking//TODO: specificate flush condition
   icacheMissQueue.io.req.bits.apply(missAddr=groupPC(s3_tlb_resp.paddr),missIdx=s3_idx,missWaymask=s3_wayMask,source=cacheID.U(2.W))
   icacheMissQueue.io.resp.ready := io.resp.ready
   icacheMissQueue.io.flush := io.flush(1)
 
   when(icacheMissQueue.io.req.fire()){blocking := true.B}
-  .elsewhen(icacheMissQueue.io.resp.fire() && isICacheResp){blocking := false.B}
+  .elsewhen(blocking && ((icacheMissQueue.io.resp.fire() && isICacheResp) || io.flush(1)) ){blocking := false.B}
 
+  XSDebug(blocking && io.flush(1),"check for icache non-blocking")
   //cache flush register
   val icacheFlush = WireInit(false.B)
   val cacheflushed = RegInit(false.B)

src/main/scala/xiangshan/cache/icacheMissQueue.scala

@@ -102,7 +102,6 @@ class IcacheMissEntry extends ICacheMissQueueModule
 
     io.req.ready := state === s_idle
     io.mem_acquire.valid := state === s_memReadReq
-    io.resp.valid := state === s_wait_resp
 
     //flush register
     val needFlush = RegInit(false.B)
@@ -162,7 +161,8 @@ class IcacheMissEntry extends ICacheMissQueueModule
     io.mem_acquire.bits.addr := req.addr
     io.mem_acquire.bits.id := io.id
 
-
+    //resp to icache
+    io.resp.valid := (state === s_wait_resp) && !needFlush
 
     XSDebug("[ICache MSHR %d] (req)valid:%d  ready:%d req.addr:%x waymask:%b  || Register: req:%x  \n",io.id.asUInt,io.req.valid,io.req.ready,io.req.bits.addr,io.req.bits.waymask,req.asUInt)
     XSDebug("[ICache MSHR %d] (Info)state:%d  needFlush:%d\n",io.id.asUInt,state,needFlush)