ldu,stu,atomics: replay signal only valid

when dcahce misses and can not enter mshr.

src/main/scala/xiangshan/cache/atomics.scala

@@ -239,7 +239,7 @@ class AtomicsPipe extends DCacheModule
   // nemu use this to see whether lr sc counter is still valid
   resp.bits.meta.id := lrsc_valid
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits := resp.bits

src/main/scala/xiangshan/cache/ldu.scala

@@ -181,7 +181,7 @@ class LoadPipe extends DCacheModule
   // upper level does not need to replay request
   // they can sit in load queue and wait for refill
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits := resp.bits

src/main/scala/xiangshan/cache/stu.scala

@@ -186,7 +186,7 @@ class StorePipe extends DCacheModule
   resp.bits.data := DontCare
   resp.bits.meta := s2_req.meta
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits  := resp.bits