diff --git a/src/main/scala/xiangshan/cache/atomics.scala b/src/main/scala/xiangshan/cache/atomics.scala
index 67870e7ebdf240b502c90b0f23e9024afa01cd62..ce52ec39b595f68183b39ef4cb3379797cf9775a 100644
--- a/src/main/scala/xiangshan/cache/atomics.scala
+++ b/src/main/scala/xiangshan/cache/atomics.scala
@@ -239,7 +239,7 @@ class AtomicsPipe extends DCacheModule
   // nemu use this to see whether lr sc counter is still valid
   resp.bits.meta.id := lrsc_valid
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits := resp.bits
diff --git a/src/main/scala/xiangshan/cache/ldu.scala b/src/main/scala/xiangshan/cache/ldu.scala
index 73e76de352726f6e1907e76c7059bde066350b40..72adaa60e1d9492f17f84a4184ca8e7237d0f9cb 100644
--- a/src/main/scala/xiangshan/cache/ldu.scala
+++ b/src/main/scala/xiangshan/cache/ldu.scala
@@ -181,7 +181,7 @@ class LoadPipe extends DCacheModule
   // upper level does not need to replay request
   // they can sit in load queue and wait for refill
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits := resp.bits
diff --git a/src/main/scala/xiangshan/cache/stu.scala b/src/main/scala/xiangshan/cache/stu.scala
index 661d24da7e62c9b9a5968676a50b49b26b7198f8..18237d9ae96d4035ed42e8c366a120c995964d33 100644
--- a/src/main/scala/xiangshan/cache/stu.scala
+++ b/src/main/scala/xiangshan/cache/stu.scala
@@ -186,7 +186,7 @@ class StorePipe extends DCacheModule
   resp.bits.data := DontCare
   resp.bits.meta := s2_req.meta
   resp.bits.miss := !s2_hit || s2_nack
-  resp.bits.replay := !io.miss_req.fire() || s2_nack
+  resp.bits.replay := resp.bits.miss && (!io.miss_req.fire() || s2_nack)
 
   io.lsu.resp.valid := resp.valid
   io.lsu.resp.bits  := resp.bits