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体验新版 GitCode,发现更多精彩内容 >>
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43c072e7
编写于
7月 01, 2020
作者:
Z
zhanglinjuan
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
fix target in btb entry
上级
78142b60
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
3 addition
and
1 deletion
+3
-1
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+1
-0
src/main/scala/xiangshan/backend/exu/Alu.scala
src/main/scala/xiangshan/backend/exu/Alu.scala
+1
-0
src/main/scala/xiangshan/frontend/BPU.scala
src/main/scala/xiangshan/frontend/BPU.scala
+1
-1
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
43c072e7
...
@@ -59,6 +59,7 @@ class MicroOp extends CfCtrl {
...
@@ -59,6 +59,7 @@ class MicroOp extends CfCtrl {
class
Redirect
extends
XSBundle
{
class
Redirect
extends
XSBundle
{
val
pc
=
UInt
(
VAddrBits
.
W
)
// wrongly predicted pc
val
pc
=
UInt
(
VAddrBits
.
W
)
// wrongly predicted pc
val
target
=
UInt
(
VAddrBits
.
W
)
val
target
=
UInt
(
VAddrBits
.
W
)
val
brTarget
=
UInt
(
VAddrBits
.
W
)
val
brTag
=
UInt
(
BrTagWidth
.
W
)
val
brTag
=
UInt
(
BrTagWidth
.
W
)
val
_type
=
UInt
(
2.
W
)
val
_type
=
UInt
(
2.
W
)
val
taken
=
Bool
()
val
taken
=
Bool
()
...
...
src/main/scala/xiangshan/backend/exu/Alu.scala
浏览文件 @
43c072e7
...
@@ -103,6 +103,7 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) {
...
@@ -103,6 +103,7 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) {
io
.
out
.
bits
.
redirectValid
:=
io
.
out
.
valid
&&
isBru
//isBranch
io
.
out
.
bits
.
redirectValid
:=
io
.
out
.
valid
&&
isBru
//isBranch
io
.
out
.
bits
.
redirect
.
pc
:=
uop
.
cf
.
pc
io
.
out
.
bits
.
redirect
.
pc
:=
uop
.
cf
.
pc
io
.
out
.
bits
.
redirect
.
target
:=
Mux
(!
taken
&&
isBranch
,
pcLatchSlot
,
target
)
io
.
out
.
bits
.
redirect
.
target
:=
Mux
(!
taken
&&
isBranch
,
pcLatchSlot
,
target
)
io
.
out
.
bits
.
redirect
.
brTarget
:=
target
io
.
out
.
bits
.
redirect
.
brTag
:=
uop
.
brTag
io
.
out
.
bits
.
redirect
.
brTag
:=
uop
.
brTag
io
.
out
.
bits
.
redirect
.
_type
:=
LookupTree
(
func
,
RV32I_BRUInstr
.
bruFuncTobtbTypeTable
)
io
.
out
.
bits
.
redirect
.
_type
:=
LookupTree
(
func
,
RV32I_BRUInstr
.
bruFuncTobtbTypeTable
)
io
.
out
.
bits
.
redirect
.
taken
:=
taken
io
.
out
.
bits
.
redirect
.
taken
:=
taken
...
...
src/main/scala/xiangshan/frontend/BPU.scala
浏览文件 @
43c072e7
...
@@ -168,7 +168,7 @@ class BPU extends XSModule {
...
@@ -168,7 +168,7 @@ class BPU extends XSModule {
btbWrite
.
valid
:=
true
.
B
btbWrite
.
valid
:=
true
.
B
btbWrite
.
tag
:=
btbAddr
.
getTag
(
redirectLatch
.
pc
)
btbWrite
.
tag
:=
btbAddr
.
getTag
(
redirectLatch
.
pc
)
btbWrite
.
_type
:=
redirectLatch
.
_type
btbWrite
.
_type
:=
redirectLatch
.
_type
btbWrite
.
target
:=
redirectLatch
.
t
arget
btbWrite
.
target
:=
redirectLatch
.
brT
arget
val
oldPred
=
PriorityMux
(
btbWriteWay
.
asTypeOf
(
Vec
(
BtbWays
,
Bool
())),
btbUpdateRead
.
map
{
e
=>
e
.
pred
})
val
oldPred
=
PriorityMux
(
btbWriteWay
.
asTypeOf
(
Vec
(
BtbWays
,
Bool
())),
btbUpdateRead
.
map
{
e
=>
e
.
pred
})
val
newPred
=
Mux
(
redirectLatch
.
taken
,
Mux
(
oldPred
===
"b11"
.
U
,
"b11"
.
U
,
oldPred
+
1.
U
),
val
newPred
=
Mux
(
redirectLatch
.
taken
,
Mux
(
oldPred
===
"b11"
.
U
,
"b11"
.
U
,
oldPred
+
1.
U
),
Mux
(
oldPred
===
"b00"
.
U
,
"b00"
.
U
,
oldPred
-
1.
U
))
Mux
(
oldPred
===
"b00"
.
U
,
"b00"
.
U
,
oldPred
-
1.
U
))
...
...
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