fix target in btb entry

src/main/scala/xiangshan/Bundle.scala

@@ -59,6 +59,7 @@ class MicroOp extends CfCtrl {
 class Redirect extends XSBundle {
   val pc = UInt(VAddrBits.W) // wrongly predicted pc
   val target = UInt(VAddrBits.W)
+  val brTarget = UInt(VAddrBits.W)
   val brTag = UInt(BrTagWidth.W)
   val _type = UInt(2.W)
   val taken = Bool()

src/main/scala/xiangshan/backend/exu/Alu.scala

@@ -103,6 +103,7 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) {
   io.out.bits.redirectValid := io.out.valid && isBru//isBranch
   io.out.bits.redirect.pc := uop.cf.pc
   io.out.bits.redirect.target := Mux(!taken && isBranch, pcLatchSlot, target)
+  io.out.bits.redirect.brTarget := target
   io.out.bits.redirect.brTag := uop.brTag
   io.out.bits.redirect._type := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
   io.out.bits.redirect.taken := taken

src/main/scala/xiangshan/frontend/BPU.scala

@@ -168,7 +168,7 @@ class BPU extends XSModule {
   btbWrite.valid := true.B
   btbWrite.tag := btbAddr.getTag(redirectLatch.pc)
   btbWrite._type := redirectLatch._type
-  btbWrite.target := redirectLatch.target
+  btbWrite.target := redirectLatch.brTarget
   val oldPred = PriorityMux(btbWriteWay.asTypeOf(Vec(BtbWays, Bool())), btbUpdateRead.map{ e => e.pred })
   val newPred = Mux(redirectLatch.taken, Mux(oldPred === "b11".U, "b11".U, oldPred + 1.U),
     Mux(oldPred === "b00".U, "b00".U, oldPred - 1.U))