From 41ef9492f7623e1165410ae3f9283552262ae386 Mon Sep 17 00:00:00 2001 From: LinJiawei Date: Tue, 30 Jun 2020 11:33:06 +0800 Subject: [PATCH] Fix freelist bug --- .../scala/xiangshan/backend/exu/Alu.scala | 3 --- .../scala/xiangshan/backend/exu/Bru.scala | 3 --- .../scala/xiangshan/backend/exu/Exu.scala | 2 ++ .../xiangshan/backend/rename/FreeList.scala | 2 +- .../scala/xiangshan/backend/roq/Roq.scala | 23 ++++++++++++------- 5 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/main/scala/xiangshan/backend/exu/Alu.scala b/src/main/scala/xiangshan/backend/exu/Alu.scala index 846713478..7d87f17f6 100644 --- a/src/main/scala/xiangshan/backend/exu/Alu.scala +++ b/src/main/scala/xiangshan/backend/exu/Alu.scala @@ -109,9 +109,6 @@ class Alu extends Exu(alu.litValue(), hasRedirect = true) { io.out.valid := valid io.out.bits.uop <> io.in.bits.uop io.out.bits.data := Mux(isJump, pcLatchSlot, aluRes) - - io.dmem <> DontCare - io.out.bits.debug.isMMIO := DontCare // FIXME: dont know how to do with it XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n", io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag, uop.brMask) diff --git a/src/main/scala/xiangshan/backend/exu/Bru.scala b/src/main/scala/xiangshan/backend/exu/Bru.scala index d59b38122..5e335c5f2 100644 --- a/src/main/scala/xiangshan/backend/exu/Bru.scala +++ b/src/main/scala/xiangshan/backend/exu/Bru.scala @@ -57,9 +57,6 @@ class Bru extends Exu(FuType.bru.litValue(), writeFpRf = true, hasRedirect = tru io.out.bits.uop <> io.in.bits.uop io.out.bits.data := res - io.dmem <> DontCare - io.out.bits.debug.isMMIO := DontCare - // NOTE: the debug info is for one-cycle exec, if FMV needs multi-cycle, may needs change it XSDebug(io.in.valid, "In(%d %d) Out(%d %d) Redirect:(%d %d %d) brTag:%x, brMask:%x\n", io.in.valid, io.in.ready, io.out.valid, io.out.ready, io.redirect.valid, io.redirect.bits.isException, redirectHit, io.redirect.bits.brTag, uop.brMask) diff --git a/src/main/scala/xiangshan/backend/exu/Exu.scala b/src/main/scala/xiangshan/backend/exu/Exu.scala index efd18262e..53433d843 100644 --- a/src/main/scala/xiangshan/backend/exu/Exu.scala +++ b/src/main/scala/xiangshan/backend/exu/Exu.scala @@ -38,6 +38,8 @@ abstract class Exu val hasRedirect: Boolean = false ) extends XSModule { val io = IO(new ExuIO) + io.dmem <> DontCare + io.out.bits.debug.isMMIO := false.B } class Mul extends Exu(FuType.mul.litValue()) with NeedImpl{ diff --git a/src/main/scala/xiangshan/backend/rename/FreeList.scala b/src/main/scala/xiangshan/backend/rename/FreeList.scala index ec99ca8b0..72e4a48bf 100644 --- a/src/main/scala/xiangshan/backend/rename/FreeList.scala +++ b/src/main/scala/xiangshan/backend/rename/FreeList.scala @@ -75,8 +75,8 @@ class FreeList extends XSModule with HasFreeListConsts { ){ canAlloc := !empty pdest := freeList(headPtrNext.value) - allocPtr := headPtrNext headPtrNext = headPtrNext + (allocReq && canAlloc) + allocPtr := headPtrNext empty = isEmpty(headPtrNext, tailPtr) } diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala index c9c5b07da..6e1ef529e 100644 --- a/src/main/scala/xiangshan/backend/roq/Roq.scala +++ b/src/main/scala/xiangshan/backend/roq/Roq.scala @@ -19,6 +19,8 @@ class Roq(implicit val p: XSConfig) extends XSModule { val scommit = Output(UInt(3.W)) }) + val numWbPorts = io.exeWbResults.length + val microOp = Mem(RoqSize, new MicroOp) // val brMask = Reg(Vec(RoqSize, UInt(BrqSize.W))) val valid = RegInit(VecInit(List.fill(RoqSize)(false.B))) @@ -66,9 +68,9 @@ class Roq(implicit val p: XSConfig) extends XSModule { } // Writeback - val firedWriteback = VecInit((0 until exuConfig.ExuCnt).map(io.exeWbResults(_).fire())).asUInt + val firedWriteback = VecInit((0 until numWbPorts).map(io.exeWbResults(_).fire())).asUInt XSInfo(PopCount(firedWriteback) > 0.U, "writebacked %d insts\n", PopCount(firedWriteback)) - for(i <- 0 until exuConfig.ExuCnt){ + for(i <- 0 until numWbPorts){ when(io.exeWbResults(i).fire()){ writebacked(io.exeWbResults(i).bits.uop.roqIdx) := true.B exuData(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.data @@ -96,7 +98,17 @@ class Roq(implicit val p: XSConfig) extends XSModule { archRF(microOp(ringBufferTail+i.U).ctrl.ldest) := exuData(ringBufferTail+i.U) } // for difftest when(io.commits(i).valid){valid(ringBufferTail+i.U) := false.B} - XSInfo(io.commits(i).valid, "retired pc %x wen %d ldst %d data %x\n", microOp(ringBufferTail+i.U).cf.pc, microOp(ringBufferTail+i.U).ctrl.rfWen, microOp(ringBufferTail+i.U).ctrl.ldest, exuData(ringBufferTail+i.U)) + XSInfo(io.commits(i).valid, + "retired pc %x wen %d ldst %d data %x\n", + microOp(ringBufferTail+i.U).cf.pc, + microOp(ringBufferTail+i.U).ctrl.rfWen, + microOp(ringBufferTail+i.U).ctrl.ldest, + exuData(ringBufferTail+i.U) + ) + XSInfo(io.commits(i).valid && exuDebug(ringBufferTail+i.U).isMMIO, + "difftest skiped pc0x%x\n", + microOp(ringBufferTail+i.U).cf.pc + ) }.otherwise{//state === s_walk io.commits(i).valid := valid(ringBufferWalk+i.U) && shouldWalkVec(i) io.commits(i).bits.uop := microOp(ringBufferWalk+i.U) @@ -125,11 +137,6 @@ class Roq(implicit val p: XSConfig) extends XSModule { val retireCounter = Mux(state === s_idle, PopCount(validCommit), 0.U) XSInfo(retireCounter > 0.U, "retired %d insts\n", retireCounter) - for(i <- 0 until CommitWidth) { - XSInfo(io.commits(i).valid, "retired pc at commmit(%d) is: %d 0x%x\n", - i.U, ringBufferTail+i.U, microOp(ringBufferTail+i.U).cf.pc) - XSInfo(io.commits(i).valid && exuDebug(ringBufferTail+i.U).isMMIO, "difftest skiped pc0x%x\n", microOp(ringBufferTail+i.U).cf.pc) - } // commit store to lsu val validScommit = WireInit(VecInit((0 until CommitWidth).map(i => io.commits(i).valid && microOp(ringBufferTail+i.U).ctrl.fuType === FuType.ldu && microOp(ringBufferTail+i.U).ctrl.fuOpType(3)))) //FIXIT -- GitLab