TLB: add multi-port support for blocking tlb

src/main/scala/xiangshan/cache/TLB.scala

@@ -615,14 +615,16 @@ object TLB {
         // tlb.io.requestor(i).resp.ready := in(i).resp.ready
       }
     } else { // itlb
-      require(width == 1)
-      tlb.io.requestor(0).req.valid := in(0).req.valid
-      tlb.io.requestor(0).req.bits := in(0).req.bits
-      in(0).req.ready := !tlb.io.requestor(0).resp.bits.miss && in(0).resp.ready && tlb.io.requestor(0).req.ready
-
-      in(0).resp.valid := tlb.io.requestor(0).resp.valid && !tlb.io.requestor(0).resp.bits.miss
-      in(0).resp.bits := tlb.io.requestor(0).resp.bits
-      tlb.io.requestor(0).resp.ready := in(0).resp.ready
+      //require(width == 1)
+      (0 until width).map{ i =>
+        tlb.io.requestor(i).req.valid := in(i).req.valid
+        tlb.io.requestor(i).req.bits := in(i).req.bits
+        in(i).req.ready := !tlb.io.requestor(i).resp.bits.miss && in(i).resp.ready && tlb.io.requestor(i).req.ready
+
+        in(i).resp.valid := tlb.io.requestor(i).resp.valid && !tlb.io.requestor(i).resp.bits.miss
+        in(i).resp.bits := tlb.io.requestor(i).resp.bits
+        tlb.io.requestor(i).resp.ready := in(i).resp.ready
+      }
     }
 
     tlb.io.ptw

src/main/scala/xiangshan/decoupled-frontend/Frontend.scala

@@ -68,7 +68,14 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   val icacheMeta      = Module(new ICacheMetaArray)
   val icacheData      = Module(new ICacheDataArray)
   val icacheMissQueue = Module(new ICacheMissQueue)
-  val itlb            = Module(new TLB(Width = 2, isDtlb = false))         
+  io.ptw <> TLB(
+    in = Seq(ifu.io.iTLBInter(0), ifu.io.iTLBInter(1)),
+    sfence = io.sfence,
+    csr = io.tlbCsr,
+    width = 2,
+    isDtlb = false,
+    shouldBlock = true
+  )  
   //TODO: modules need to be removed
   val instrUncache = outer.instrUncache.module
   val l1plusPrefetcher = Module(new L1plusPrefetcher)
@@ -85,11 +92,6 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   ifu.io.icacheInter.fromIMeta  <>      icacheMeta.io.readResp
   ifu.io.icacheInter.toIData    <>      icacheData.io.read
   ifu.io.icacheInter.fromIData  <>      icacheData.io.readResp
-  //IFU-ITLB
-  ifu.io.iTLBInter              <>      itlb.io.requestor
-  io.ptw                        <>      itlb.io.ptw
-  io.sfence                     <>      itlb.io.sfence
-  io.tlbCsr                     <>      itlb.io.csr
 
 
   for(i <- 0 until 2){

src/main/scala/xiangshan/decoupled-frontend/IFU.scala

@@ -44,7 +44,7 @@ class NewIFUIO(implicit p: Parameters) extends XSBundle {
   val ftqInter        = new FtqInterface  
   val icacheInter     = new ICacheInterface 
   val toIbuffer       = Decoupled(new FetchToIBuffer)
-  val iTLBInter       = Vec(2, new TlbRequestIO) 
+  val iTLBInter       = Vec(2, new BlockTlbRequestIO) 
 }
 
 // record the situation in which fallThruAddr falls into
@@ -60,7 +60,6 @@ class IfuToPreDecode(implicit p: Parameters) extends XSBundle {
   val startAddr     = UInt(VAddrBits.W)
   val fallThruAddr  = UInt(VAddrBits.W)
   val ftqOffset     = Valid(UInt(log2Ceil(PredictWidth).W))
-  val startRange    = Vec(PredictWidth, Bool())
   val target        = UInt(VAddrBits.W)
   val pageFault     = Vec(2, Bool())
   val accessFault   = Vec(2, Bool())
@@ -374,12 +373,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with HasICacheParameters
   preDecoderIn.target        :=  f2_ftq_req.target
   preDecoderIn.oversize      :=  f2_ftq_req.oversize
   preDecoderIn.lastHalfMatch :=  f2_lastHalfMatch
-<<<<<<< HEAD
-  preDecoderIn.startRange    :=  f2_ldreplay_valids.asTypeOf( Vec(PredictWidth, Bool()) )
   preDecoderIn.pageFault     :=  f2_except_pf  
   preDecoderIn.accessFault   :=  f2_except_af
-=======
->>>>>>> decoupled-frontend
 
   predecodeOutValid          :=  fetchFinish
 

src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala

@@ -114,13 +114,15 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{
 
   val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i))))  
                        else         VecInit((0 until PredictWidth).map(i => data(i)))
+  
+  val nextLinePC =  align(pcStart, 64) + 64.U
 
   for (i <- 0 until PredictWidth) {
     //TODO: Terrible timing for pc comparing
-    val hasPageFault   = instRange(i) && validStart(i) && ((io.out.pc(i) < align(realEndPC, 64) && pageFault(0))   || (io.out.pc(i) > align(realEndPC, 64) && pageFault(1)))
-    val hasAccessFault = instRange(i) && validStart(i) && ((io.out.pc(i) < align(realEndPC, 64) && accessFault(0)) || (io.out.pc(i) > align(realEndPC, 64) && accessFault(1)))
+    val hasPageFault   = validStart(i) && ((io.out.pc(i) < nextLinePC && pageFault(0))   || (io.out.pc(i) > nextLinePC && pageFault(1)))
+    val hasAccessFault = validStart(i) && ((io.out.pc(i) < nextLinePC && accessFault(0)) || (io.out.pc(i) > nextLinePC && accessFault(1)))
     val exception      = hasPageFault || hasAccessFault
-    val inst           = Mux(exception,NOP,WireInit(rawInsts(i)))
+    val inst           = Mux(exception, NOP, WireInit(rawInsts(i)))
     val expander       = Module(new RVCExpander)
 
     val isFirstInBlock = i.U === 0.U

src/main/scala/xiangshan/decoupled-frontend/uBTB.scala

@@ -220,7 +220,7 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   val read_resps = banks.read_resp
 
   XSDebug(p"uBTB entry, read_pc=${Hexadecimal(s1_pc)}\n")
-  XSDebug(p"v=${read_resps.valid}, brValids=${Binary(read_resps.brValids.asUInt)}, jmpValid=${read_resps.jmpValid}, pred0=${Binary(read_resps.pred(0).asUInt)}, pred1=${Binary(read_resps.pred(1).asUInt)}, hit=${read_resps.hit}\n")
+  //XSDebug(p"v=${read_resps.valid}, brValids=${Binary(read_resps.brValids.asUInt)}, jmpValid=${read_resps.jmpValid}, pred0=${Binary(read_resps.pred(0).asUInt)}, pred1=${Binary(read_resps.pred(1).asUInt)}, hit=${read_resps.hit}\n")
   // XSDebug(p"v=${read_resps.valid}, brValids=${Binary(read_resps.brValids.asUInt)}, jmpValid=${read_resps.jmpValid}, pred0=${Binary(read_resps.pred(0).asUInt)}, pred1=${Binary(read_resps.pred(1).asUInt)}, hit=${read_resps.hit}\n")
   // XSDebug(p"v=${read_resps.valid}, brValids=${Binary(read_resps.brValids.asUInt)}, jmpValid=${read_resps.jmpValid}, pred0=${Binary(read_resps.pred(0).asUInt)}, hit=${read_resps.hit}\n")