Merge pull request #63 from RISCVERS/dev-temp-lsu

Lsu: add sbuffer to naive Lsu

src/main/scala/xiangshan/Bundle.scala

@@ -91,6 +91,7 @@ class ExuIO extends XSBundle {
 
   // for Lsu
   val dmem = new SimpleBusUC
+  val scommit = Input(UInt(3.W))
 }
 
 class RoqCommit extends XSBundle {

src/main/scala/xiangshan/backend/Backend.scala

@@ -84,6 +84,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
   // })
 
   lsuExeUnits.foreach(_.io.dmem <> io.dmem)
+  lsuExeUnits.foreach(_.io.scommit <> roq.io.scommit)
 
   io.frontend.redirect <> redirect
   io.frontend.commits <> roq.io.commits

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -106,6 +106,7 @@ trait HasExeUnits{
   val bjUnits = bruExeUnit +: aluExeUnits
 
   exeUnits.foreach(_.io.dmem := DontCare)
+  exeUnits.foreach(_.io.scommit := DontCare)
 }
 
 class WriteBackArbMtoN(m: Int, n: Int) extends XSModule {

src/main/scala/xiangshan/backend/exu/Lsu.scala

@@ -42,6 +42,15 @@ object LSUOpType {
   def atomD = "011".U
 }
 
+class StoreQueueEntry extends XSBundle{
+  val src1  = UInt(XLEN.W)
+  val src2  = UInt(XLEN.W)
+  val src3  = UInt(XLEN.W)
+  val wdata = UInt(XLEN.W)
+  val func  = UInt(6.W)
+  val brMask = UInt(BrqSize.W) //FIXIT
+}
+
 class Lsu extends Exu(
   FuType.ldu.litValue(),
   readIntRf = true,
@@ -51,7 +60,29 @@ class Lsu extends Exu(
 ) with NeedImpl {
   override def toString: String = "Lsu"
 
-  val (valid, src1, src2, wdata, func) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.src3, io.in.bits.uop.ctrl.fuOpType)
+  // store buffer
+  val stqData = Reg(Vec(8, new StoreQueueEntry))
+  val stqValid = RegInit(VecInit(List.fill(8)(false.B)))
+  val stqPtr = Reg(Vec(8, UInt(3.W)))
+  val stqHead = RegInit(0.U(3.W))
+  val stqTail = stqPtr(0)
+  val stqCommited = RegInit(0.U(3.W))
+  val stqFull = stqHead === 7.U //stq_valid.reduce(_.valid && _.valid)
+  val emptySlot = PriorityMux(~stqValid.asUInt, VecInit(List.tabulate(CommitWidth)(_.U)))
+
+  // when retiringStore, block all input insts
+  val isStoreIn = io.in.valid && LSUOpType.isStore(io.in.bits.uop.ctrl.fuOpType)
+  val retiringStore = Wire(Bool()) //RegInit(false.B)
+  val (validIn, src1In, src2In, src3In, funcIn) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.src3, io.in.bits.uop.ctrl.fuOpType)
+  val (valid, src1, src2, wdata, func) = 
+  (
+    Mux(retiringStore, stqValid(stqTail), validIn && !isStoreIn),
+    Mux(retiringStore, stqData(stqTail).src1, src1In),
+    Mux(retiringStore, stqData(stqTail).src2, src2In),
+    Mux(retiringStore, stqData(stqTail).src3, src3In),
+    Mux(retiringStore, stqData(stqTail).func, funcIn)
+  )
+  assert(!(retiringStore && !stqValid(stqTail)))
 
   def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
     LookupTree(sizeEncode, List(
@@ -112,12 +143,41 @@ class Lsu extends Exu(
       LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN)
   ))
 
-  io.in.ready := (state === s_idle) && io.out.ready
+  io.in.ready := io.out.fire()
 
-  io.out.valid := Mux(isStore || partialLoad, state === s_partialLoad, dmem.resp.fire() && (state === s_wait_resp))
+  io.out.valid := !retiringStore && (Mux(partialLoad, state === s_partialLoad, dmem.resp.fire() && (state === s_wait_resp)) || isStoreIn)
   io.out.bits.uop <> io.in.bits.uop
   io.out.bits.data := Mux(partialLoad, rdataPartialLoad, rdata)
   // io.out.bits.debug.isMMIO := AddressSpace.isMMIO(addr) && io.out.valid
   io.out.bits.debug.isMMIO := false.B //for debug
 
+  // if store, add it to store queue
+  val stqEnqueue = valid && isStore && !stqFull
+  when(stqEnqueue){
+    stqPtr(stqHead) := emptySlot
+    stqData(emptySlot).src1 := src1In
+    stqData(emptySlot).src2 := src2In
+    stqData(emptySlot).src3 := src3In
+    stqData(emptySlot).func := funcIn
+    stqValid(emptySlot) := true.B
+  }
+
+  // if store insts have been commited, send dmem req
+  retiringStore := stqCommited > 0.U
+
+  // pop store queue if insts have been commited and dmem req fired successfully
+  val stqDequeue = retiringStore && state === s_partialLoad
+  when(stqDequeue){
+    stqValid(stqTail) := false.B
+  }
+
+  // update stqTail, stqCommited
+  stqCommited := stqCommited + io.scommit - stqDequeue
+  stqTail := stqTail + stqEnqueue - stqDequeue
+
+  XSDebug("state: %d (valid, ready): in (%d,%d) out (%d,%d)\n", state, io.in.valid, io.in.ready, io.out.valid, io.out.ready)
+  XSDebug("stqinfo: stqValid.asUInt %b stqHead %d stqTail %d stqCommited %d emptySlot %d\n", stqValid.asUInt, stqHead, stqTail, stqCommited, emptySlot)
+  XSInfo(io.dmem.req.fire() && io.dmem.req.bits.cmd =/= SimpleBusCmd.write, "[DMEM LOAD  REQ] addr 0x%x wdata 0x%x size %d\n", dmem.req.bits.addr, dmem.req.bits.wdata, dmem.req.bits.size)
+  XSInfo(io.dmem.req.fire() && io.dmem.req.bits.cmd === SimpleBusCmd.write, "[DMEM STORE REQ] addr 0x%x wdata 0x%x size %d\n", dmem.req.bits.addr, dmem.req.bits.wdata, dmem.req.bits.size)
+  XSInfo(io.dmem.resp.fire(), "[DMEM RESP] data %x\n", rdata)
 }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -15,6 +15,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     val redirect = Output(Valid(new Redirect))
     val exeWbResults = Vec(exuConfig.ExuCnt, Flipped(ValidIO(new ExuOutput)))
     val commits = Vec(CommitWidth, Valid(new RoqCommit))
+    val scommit = Output(UInt(3.W))
   })
 
   val microOp = Mem(RoqSize, new MicroOp)
@@ -75,6 +76,9 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   when(PopCount(firedWriteback) > 0.U){
     XSInfo("writebacked %d insts\n", PopCount(firedWriteback))
   }
+  for(i <- 0 until exuConfig.ExuCnt){
+    XSInfo("writebacked pc %x wen %d data %d\n", microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc, microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, io.exeWbResults(i).bits.data)
+  }
 
   // Commit uop to Rename
   for(i <- 0 until CommitWidth){
@@ -82,7 +86,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       val canCommit = if(i!=0) io.commits(i-1).valid else true.B
       io.commits(i).valid := valid(ringBufferTail+i.U) && writebacked(ringBufferTail+i.U) && canCommit
       io.commits(i).bits.uop := microOp(ringBufferTail+i.U)
-      when(microOp(i).ctrl.rfWen){ archRF(microOp(i).ctrl.ldest) := exuData(i) }
+      when(microOp(ringBufferTail+i.U).ctrl.rfWen){ archRF(microOp(ringBufferTail+i.U).ctrl.ldest) := exuData(ringBufferTail+i.U) }
       when(io.commits(i).valid){valid(ringBufferTail+i.U) := false.B}
     }.otherwise{//state === s_walk
       io.commits(i).valid := valid(ringBufferWalk+i.U) && writebacked(ringBufferWalk+i.U)
@@ -97,7 +101,11 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     ringBufferTailExtended := ringBufferTailExtended + PopCount(validCommit)
   }
   val retireCounter = Mux(state === s_idle, PopCount(validCommit), 0.U)
-  // TODO: commit store
+
+  // commit store
+  val validScommit = WireInit(VecInit((0 until CommitWidth).map(i => io.commits(i).valid && microOp(ringBufferTail+i.U).ctrl.fuType === FuType.ldu && microOp(ringBufferTail+i.U).ctrl.fuOpType(3)))) //FIXIT
+  io.scommit := PopCount(validScommit.asUInt)
+
   XSInfo(retireCounter > 0.U, "retired %d insts\n", retireCounter)
   XSInfo("")
   XSInfo(){