Exu: fix output

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -142,7 +142,6 @@ class Decoder extends XSModule with HasInstrType {
     RV32I_ALUInstr.LUI -> SrcType.reg // FIX LUI
   ))
   io.out.ctrl.src2Type := bitPatLookup(instr, src2Type, Seq(
-    RVFInstr.FDIV_S -> SrcType.imm,
     RVFInstr.FSQRT_S -> SrcType.imm,
     RVFInstr.FCLASS_S -> SrcType.imm,
     RVFInstr.FMV_X_W -> SrcType.imm,
@@ -189,6 +188,8 @@ class Decoder extends XSModule with HasInstrType {
   io.out.ctrl.noSpecExec := io.out.ctrl.isXSTrap || io.out.ctrl.fuType===FuType.csr || io.out.ctrl.fuType===FuType.mou || io.out.ctrl.fuType===FuType.fence/*noSpecExec make it sent to alu0,for roq is empty*/
   io.out.ctrl.flushPipe := io.out.ctrl.fuType===FuType.fence
 
+  io.out.ctrl.isRVF := instr(26, 25) === 0.U
+
 
   XSDebug("in:  instr=%x pc=%x excepVec=%b intrVec=%b crossPageIPFFix=%d\n",
     io.in.instr, io.in.pc, io.in.exceptionVec.asUInt, io.in.intrVec.asUInt, io.in.crossPageIPFFix)

src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala

@@ -5,31 +5,33 @@ import chisel3.util._
 import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.exu.Exu.fmacExeUnitCfg
 import xiangshan.backend.fu.fpu.fma.FMA
+import xiangshan.backend.fu.fpu._
 
 class FmacExeUnit extends Exu(fmacExeUnitCfg) {
 
   val fma = Module(new FMA)
 
   fma.io.in.valid := io.in.valid
-
+  val input = io.in.bits
+  val fmaOut = fma.io.out.bits
+  val isRVD = !io.in.bits.uop.ctrl.isRVF
+  fma.io.in.bits.src := VecInit(Seq(input.src1, input.src2, input.src3).map(src => Mux(isRVD, src, unboxF64ToF32(src))))
   fma.io.in.bits.uop := io.in.bits.uop
-  fma.io.in.bits.src(0) := io.in.bits.src1
-  fma.io.in.bits.src(1) := io.in.bits.src2
-  fma.io.in.bits.src(2) := io.in.bits.src3
   val extraInput = fma.io.in.bits.ext.get
   val frm = WireInit(0.U(3.W))
   BoringUtils.addSink(frm, "Frm")
   extraInput.rm := frm
   extraInput.op := io.in.bits.uop.ctrl.fuOpType(2, 0)
-  extraInput.isDouble := !io.in.bits.uop.ctrl.isRVF
+  extraInput.isDouble := isRVD
 
   fma.io.redirectIn := io.redirect
   fma.io.out.ready := io.out.ready
 
   io.in.ready := fma.io.in.ready
   io.out.valid := fma.io.out.valid
-  io.out.bits.uop := fma.io.out.bits.uop
-  io.out.bits.data := fma.io.out.bits.data
+  io.out.bits.uop := fmaOut.uop
+  io.out.bits.data := Mux(fmaOut.uop.ctrl.isRVF, boxF32ToF64(fmaOut.data), fmaOut.data)
+  io.out.bits.fflags := fma.io.out.bits.ext.get
   io.out.bits.redirectValid := false.B
   io.out.bits.redirect <> DontCare
 

src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala

@@ -4,10 +4,12 @@ package xiangshan.backend.exu
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
+import utils._
 import xiangshan.backend.exu.Exu.fmiscExeUnitCfg
 import xiangshan.backend.fu.fpu.{F32toF64, F64toF32, FCMP, FMV, FPUSubModuleOutput, FloatToInt}
 import xiangshan.backend.fu.fpu.divsqrt.DivSqrt
 import xiangshan.backend.fu.fpu.FPUOpType._
+import xiangshan.backend.fu.fpu._
 
 class FmiscExeUnit extends Exu(fmiscExeUnitCfg){
 
@@ -28,10 +30,13 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg){
   ).map(x => (x._1, ("b" + x._2).U))
 
   val fuOp = io.in.bits.uop.ctrl.fuOpType
-  val fu = fuOp.head(3)
-  val op = fuOp.tail(3)
+  assert(fuOp.getWidth == 7) // when fuOp's WIDTH change, here must change too
+  val fu = fuOp.head(4)
+  val op = fuOp.tail(4)
   val frm = WireInit(0.U(3.W))
   BoringUtils.addSink(frm, "Frm")
+  val isRVF = io.in.bits.uop.ctrl.isRVF
+  val (src1, src2) = (io.in.bits.src1, io.in.bits.src2)
 
   io.in.ready := Cat(subModules.map(x => fu===x._2 && x._1.io.in.ready)).orR()
 
@@ -39,25 +44,34 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg){
     case (module, fuSel) =>
       module.io.in.valid := io.in.valid && fu===fuSel
       module.io.in.bits.uop := io.in.bits.uop
-      module.io.in.bits.src(0) := io.in.bits.src1
-      module.io.in.bits.src(1) := io.in.bits.src2
+      module.io.in.bits.src(0) := Mux(isRVF || fuOp===s2d, unboxF64ToF32(src1), src1)
+      module.io.in.bits.src(1) := Mux(isRVF, unboxF64ToF32(src2), src2)
       val extraInput = module.io.in.bits.ext.get
-      extraInput.isDouble := !io.in.bits.uop.ctrl.isRVF
+      extraInput.isDouble := !isRVF
       extraInput.rm := frm
       extraInput.op := op
       module.io.redirectIn := io.redirect
   }
+  fmv.io.in.bits.src(0) := src1 // don't unbox
 
   val wbArb = Module(new Arbiter(chiselTypeOf(subModules(0)._1.io.out.bits), subModules.length))
 
   wbArb.io.in <> VecInit(subModules.map(_._1.io.out))
-
+  
   val out = wbArb.io.out
 
   out.ready := io.out.ready
   io.out.valid := out.valid
   io.out.bits.uop := out.bits.uop
-  io.out.bits.data := out.bits.data
+  io.out.bits.fflags := out.bits.ext.get
+  val outCtrl = out.bits.uop.ctrl
+  io.out.bits.data := Mux(outCtrl.isRVF && outCtrl.fpWen, 
+    boxF32ToF64(out.bits.data), 
+    Mux(outCtrl.fuOpType===fmv_f2i || outCtrl.fuOpType===f2w || outCtrl.fuOpType===f2wu,
+      SignExt(out.bits.data(31, 0), XLEN),
+      out.bits.data
+    )
+  )
   io.out.bits.redirectValid := DontCare
   io.out.bits.redirect := DontCare
 }

src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala

@@ -3,6 +3,7 @@ package xiangshan.backend.exu
 import chisel3._
 import chisel3.util._
 import chisel3.util.experimental.BoringUtils
+import xiangshan.backend.fu.fpu._
 import xiangshan.backend.fu.fpu.IntToFloatSingleCycle
 import xiangshan.backend.fu.fpu.FPUOpType._
 
@@ -11,8 +12,8 @@ class I2fExeUnit extends Exu(Exu.i2fExeUnitCfg){
   val uopIn = io.in.bits.uop
   val isDouble = !uopIn.ctrl.isRVF
   val fuOp = uopIn.ctrl.fuOpType
-  val fu = fuOp.head(3)
-  val op = fuOp.tail(3)
+  val fu = fuOp.head(4)
+  val op = fuOp.tail(4)
   val frm = WireInit(0.U(3.W))
   BoringUtils.addSink(frm, "Frm")
 
@@ -29,8 +30,12 @@ class I2fExeUnit extends Exu(Exu.i2fExeUnitCfg){
   intToFloat.io.redirectIn := io.redirect
   io.out.valid := valid
   io.out.bits.data := Mux(intToFloat.io.out.valid,
-    intToFloat.io.out.bits.data,
-    io.in.bits.src1
+    Mux(isDouble, intToFloat.io.out.bits.data, boxF32ToF64(intToFloat.io.out.bits.data)),
+    Mux(isDouble, io.in.bits.src1, boxF32ToF64(io.in.bits.src1))
+  )
+  io.out.bits.fflags := Mux(intToFloat.io.out.valid,
+    intToFloat.io.out.bits.ext.get,
+    0.U.asTypeOf(new Fflags)
   )
   io.in.ready := true.B
   io.out.bits.uop := uopIn

src/main/scala/xiangshan/backend/exu/Wbu.scala

@@ -85,10 +85,15 @@ class Wbu(exuConfigs: Array[ExuConfig]) extends XSModule{
 
   def splitN[T](in: Seq[T], n: Int): Seq[Option[Seq[T]]] = {
     require(n > 0)
-    if(in.size < n) Seq(Some(in)) ++ Seq.fill(n-1)(None)
-    else {
-      val m = in.size/n
-      Some(in.take(m)) +: splitN(in.drop(m), n-1)
+    if(n == 1){
+      return Seq(Some(in))
+    } else {
+      if(in.size < n ){
+        Seq(Some(in)) ++ Seq.fill(n-1)(None)
+      } else {
+        val m = in.size / n
+        Some(in.take(m)) +: splitN(in.drop(m), n-1)
+      }
     }
   }
 
@@ -105,12 +110,14 @@ class Wbu(exuConfigs: Array[ExuConfig]) extends XSModule{
   } else {
     val directReq = wbIntReq.filter(w => Seq(Exu.ldExeUnitCfg, Exu.aluExeUnitCfg).contains(w._2))
     val mulReq = wbIntReq.filter(w => Seq(Exu.mulExeUnitCfg, Exu.mulDivExeUnitCfg, Exu.mulDivFenceExeUnitCfg).contains(w._2))
+    println("aaa")
     val otherReq = splitN(
       wbIntReq.filterNot(w => Seq(
         Exu.ldExeUnitCfg, Exu.aluExeUnitCfg, Exu.mulDivExeUnitCfg, Exu.mulExeUnitCfg, Exu.mulDivFenceExeUnitCfg
       ).contains(w._2)),
       mulReq.size
     )
+    println("bbb")
     require(directReq.size + mulReq.size <= NRIntWritePorts)
     // alu && load: direct connect
     io.toIntRf.take(directReq.size).zip(directReq).foreach(x => directConnect(x._1, x._2._1))

src/main/scala/xiangshan/backend/fu/FunctionUnit.scala

@@ -146,7 +146,7 @@ object FunctionUnit {
     FuConfig(FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false)
 
   val fmiscCfg =
-    FuConfig(FuType.fmisc, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)
+    FuConfig(FuType.fmisc, 0, 2, writeIntRf = true, writeFpRf = true, hasRedirect = false)
 
   val fDivSqrtCfg =
     FuConfig(FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false)