Exu: connect frm and fflags

src/main/scala/xiangshan/Bundle.scala

@@ -4,6 +4,7 @@ import chisel3._
 import chisel3.util._
 import bus.simplebus._
 import xiangshan.backend.brq.BrqPtr
+import xiangshan.backend.fu.fpu.Fflags
 import xiangshan.backend.rename.FreeListPtr
 import xiangshan.frontend.PreDecodeInfo
 import xiangshan.frontend.HasBPUParameter
@@ -197,6 +198,7 @@ class ExuInput extends XSBundle {
 class ExuOutput extends XSBundle {
   val uop = new MicroOp
   val data = UInt(XLEN.W)
+  val fflags  = new Fflags
   val redirectValid = Bool()
   val redirect = new Redirect
   val brUpdate = new BranchUpdateInfo

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -53,6 +53,7 @@ abstract class Exu(val config: ExuConfig) extends XSModule {
   val io = IO(new ExuIO)
   io.dmem <> DontCare
   io.out.bits.brUpdate <> DontCare
+  io.out.bits.fflags <> DontCare
   io.out.bits.debug.isMMIO := false.B
 }
 

src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala

@@ -2,6 +2,7 @@ package xiangshan.backend.exu
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.exu.Exu.fmacExeUnitCfg
 import xiangshan.backend.fu.fpu.fma.FMA
 
@@ -16,7 +17,9 @@ class FmacExeUnit extends Exu(fmacExeUnitCfg) {
   fma.io.in.bits.src(1) := io.in.bits.src2
   fma.io.in.bits.src(2) := io.in.bits.src3
   val extraInput = fma.io.in.bits.ext.get
-  extraInput.rm := DontCare
+  val frm = WireInit(0.U(3.W))
+  BoringUtils.addSink(frm, "Frm")
+  extraInput.rm := frm
   extraInput.op := io.in.bits.uop.ctrl.fuOpType(2, 0)
   extraInput.isDouble := !io.in.bits.uop.ctrl.isRVF
 

src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala

@@ -3,6 +3,7 @@ package xiangshan.backend.exu
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.exu.Exu.fmiscExeUnitCfg
 import xiangshan.backend.fu.fpu.{F32toF64, F64toF32, FCMP, FMV, FPUSubModuleOutput, FloatToInt}
 import xiangshan.backend.fu.fpu.divsqrt.DivSqrt
@@ -29,6 +30,8 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg){
   val fuOp = io.in.bits.uop.ctrl.fuOpType
   val fu = fuOp.head(3)
   val op = fuOp.tail(3)
+  val frm = WireInit(0.U(3.W))
+  BoringUtils.addSink(frm, "Frm")
 
   io.in.ready := Cat(subModules.map(x => fu===x._2 && x._1.io.in.ready)).orR()
 
@@ -40,7 +43,7 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg){
       module.io.in.bits.src(1) := io.in.bits.src2
       val extraInput = module.io.in.bits.ext.get
       extraInput.isDouble := !io.in.bits.uop.ctrl.isRVF
-      extraInput.rm := DontCare
+      extraInput.rm := frm
       extraInput.op := op
       module.io.redirectIn := io.redirect
   }

src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala

@@ -2,6 +2,7 @@ package xiangshan.backend.exu
 
 import chisel3._
 import chisel3.util._
+import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.fu.fpu.IntToFloatSingleCycle
 import xiangshan.backend.fu.fpu.FPUOpType._
 
@@ -12,11 +13,14 @@ class I2fExeUnit extends Exu(Exu.i2fExeUnitCfg){
   val fuOp = uopIn.ctrl.fuOpType
   val fu = fuOp.head(3)
   val op = fuOp.tail(3)
+  val frm = WireInit(0.U(3.W))
+  BoringUtils.addSink(frm, "Frm")
+
   val valid = io.in.valid && !uopIn.needFlush(io.redirect)
   val intToFloat = Module(new IntToFloatSingleCycle)
   val extraInput = intToFloat.io.in.bits.ext.get
   extraInput.isDouble := isDouble
-  extraInput.rm := DontCare
+  extraInput.rm := frm
   extraInput.op := op
   intToFloat.io.out.ready := io.out.ready
   intToFloat.io.in.valid := valid && fu===("b"+FU_I2F).U

src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala

 package xiangshan.backend.exu
 
 import chisel3._
+import chisel3.util.experimental.BoringUtils
 import xiangshan.{ExuOutput, FuType}
 import xiangshan.backend.fu.{CSR, Jump}
 import xiangshan.backend.decode.isa._
+import xiangshan.backend.fu.fpu.Fflags
 import utils._
 
 class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
@@ -32,13 +34,24 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
   jumpExuOut.uop := uop
   jumpExuOut.data := jmp.io.out.bits.data
   jumpExuOut.brUpdate := jumpExtraOut.brUpdate
+  jumpExuOut.fflags := DontCare
   jumpExuOut.redirect := jumpExtraOut.redirect
   jumpExuOut.redirectValid := jumpExtraOut.redirectValid
   jumpExuOut.debug := DontCare
 
 
+  val fflags = WireInit(0.U.asTypeOf(new Fflags))
+  val dirty_fs = WireInit(false.B)
+  BoringUtils.addSink(fflags, "Fflags")
+  BoringUtils.addSink(dirty_fs, "DirtyFs")
+  val frm = WireInit(0.U(3.W))
+  frm := csr.io.fpu_csr.frm
+  BoringUtils.addSource(frm, "Frm")
+
   csr.io.cfIn := io.in.bits.uop.cf
-  csr.io.fpu_csr := DontCare
+  csr.io.fpu_csr.fflags := fflags
+  csr.io.fpu_csr.isIllegal := false.B // TODO: check illegal rounding mode
+  csr.io.fpu_csr.dirty_fs := dirty_fs
   csr.io.exception <> io.exception
   csr.io.instrValid := DontCare
   csr.io.out.ready := io.out.ready
@@ -53,6 +66,7 @@ class JmpExeUnit extends Exu(Exu.jmpExeUnitCfg) {
   csrExuOut.uop.cf := csr.io.cfOut
   csrExuOut.uop.ctrl.flushPipe := csr.io.flushPipe
   csrExuOut.data := csrOut
+  csrExuOut.fflags := DontCare
   csrExuOut.redirectValid := csr.io.redirectOutValid
   csrExuOut.redirect.brTag := uop.brTag
   csrExuOut.redirect.isException := false.B

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -7,6 +7,7 @@ import xiangshan._
 import utils._
 import chisel3.util.experimental.BoringUtils
 import xiangshan.backend.LSUOpType
+import xiangshan.backend.fu.fpu.Fflags
 
 
 class Roq extends XSModule {
@@ -30,6 +31,7 @@ class Roq extends XSModule {
   val flag = RegInit(VecInit(List.fill(RoqSize)(false.B)))
   val writebacked = Reg(Vec(RoqSize, Bool()))
 
+  val exuFflags = Mem(RoqSize, new Fflags)
   val exuData = Reg(Vec(RoqSize, UInt(XLEN.W)))//for debug
   val exuDebug = Reg(Vec(RoqSize, new DebugBundle))//for debug
 
@@ -92,6 +94,7 @@ class Roq extends XSModule {
       microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe
       microOp(wbIdx).diffTestDebugLrScValid := io.exeWbResults(i).bits.uop.diffTestDebugLrScValid
       exuData(wbIdx) := io.exeWbResults(i).bits.data
+      exuFflags(wbIdx) := io.exeWbResults(i).bits.fflags
       exuDebug(wbIdx) := io.exeWbResults(i).bits.debug
 
       val debugUop = microOp(wbIdx)
@@ -150,6 +153,9 @@ class Roq extends XSModule {
 
   val storeCommitVec = WireInit(VecInit(Seq.fill(CommitWidth)(false.B)))
   val cfiCommitVec = WireInit(VecInit(Seq.fill(CommitWidth)(false.B)))
+  // wiring to csr
+  val fflags = WireInit(0.U.asTypeOf(new Fflags))
+  val dirty_fs = WireInit(false.B)
   for(i <- 0 until CommitWidth){
     io.commits(i) := DontCare
     switch(state){
@@ -169,15 +175,28 @@ class Roq extends XSModule {
         cfiCommitVec(i) := io.commits(i).valid &&
           !commitUop.cf.brUpdate.pd.notCFI
 
+        val commitFflags = exuFflags(commitIdx)
+        when(io.commits(i).valid){
+          when(commitFflags.asUInt.orR()){
+            // update fflags
+            fflags := exuFflags(commitIdx)
+          }
+          when(commitUop.ctrl.fpWen){
+            // set fs to dirty
+            dirty_fs := true.B
+          }
+        }
+
         when(io.commits(i).valid){v := false.B}
         XSInfo(io.commits(i).valid,
-          "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x\n",
+          "retired pc %x wen %d ldest %d pdest %x old_pdest %x data %x fflags: %b\n",
           commitUop.cf.pc,
           commitUop.ctrl.rfWen,
           commitUop.ctrl.ldest,
           commitUop.pdest,
           commitUop.old_pdest,
-          exuData(commitIdx)
+          exuData(commitIdx),
+          exuFflags(commitIdx).asUInt
         )
         XSInfo(io.commits(i).valid && exuDebug(commitIdx).isMMIO,
           "difftest skiped pc0x%x\n",
@@ -218,6 +237,9 @@ class Roq extends XSModule {
     io.commits(i).bits.isWalk := state =/= s_idle
   }
 
+  BoringUtils.addSource(fflags, "Fflags")
+  BoringUtils.addSource(dirty_fs, "DirtyFs")
+
   val validCommit = io.commits.map(_.valid)
   when(state===s_walk) {
     //exit walk state when all roq entry is commited

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -279,6 +279,7 @@ class LoadUnit extends XSModule {
   val hitLoadOut = Wire(Decoupled(new ExuOutput))
   hitLoadOut.bits.uop := l5_in.bits.uop
   hitLoadOut.bits.data := rdataPartialLoad
+  hitLoadOut.bits.fflags := DontCare
   hitLoadOut.bits.redirectValid := false.B
   hitLoadOut.bits.redirect := DontCare
   hitLoadOut.bits.brUpdate := DontCare

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -7,6 +7,7 @@ import xiangshan._
 import xiangshan.cache._
 import xiangshan.cache.{DCacheLoadIO, TlbRequestIO, MemoryOpConstants}
 import xiangshan.backend.LSUOpType
+import xiangshan.backend.fu.fpu.boxF32ToF64
 
 class LsRoqEntry extends XSBundle {
   val vaddr = UInt(VAddrBits.W) // TODO: need opt
@@ -269,6 +270,7 @@ class Lsroq extends XSModule {
         LSUOpType.lb   -> SignExt(rdataSel(7, 0) , XLEN),
         LSUOpType.lh   -> SignExt(rdataSel(15, 0), XLEN),
         LSUOpType.lw   -> SignExt(rdataSel(31, 0), XLEN),
+        LSUOpType.flw  -> boxF32ToF64(rdataSel(31, 0)),
         LSUOpType.ld   -> SignExt(rdataSel(63, 0), XLEN),
         LSUOpType.lbu  -> ZeroExt(rdataSel(7, 0) , XLEN),
         LSUOpType.lhu  -> ZeroExt(rdataSel(15, 0), XLEN),
@@ -277,6 +279,7 @@ class Lsroq extends XSModule {
     io.ldout(i).bits.uop := uop(loadWbSel(i))
     io.ldout(i).bits.uop.cf.exceptionVec := data(loadWbSel(i)).exception.asBools
     io.ldout(i).bits.data := rdataPartialLoad
+    io.ldout(i).bits.fflags := DontCare
     io.ldout(i).bits.redirectValid := false.B
     io.ldout(i).bits.redirect := DontCare
     io.ldout(i).bits.brUpdate := DontCare
@@ -312,6 +315,7 @@ class Lsroq extends XSModule {
     io.stout(i).bits.uop := uop(storeWbSel(i))
     io.stout(i).bits.uop.cf.exceptionVec := data(storeWbSel(i)).exception.asBools
     io.stout(i).bits.data := data(storeWbSel(i)).data
+    io.stout(i).bits.fflags := DontCare
     io.stout(i).bits.redirectValid := false.B
     io.stout(i).bits.redirect := DontCare
     io.stout(i).bits.brUpdate := DontCare