Merge branch 'master' into issuequeue

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import utils.{GTimer}
+import xiangshan.utils.{XSDebug, XSInfo}
 
 case class DP1Config
 (
@@ -43,14 +43,10 @@ class Dispatch1 extends XSModule{
                     (io.toLsDq(i).ready  && FuType.isMemExu(io.fromRename(i).bits.ctrl.fuType))
     enq_valid(i) := io.toIntDq(i).valid || io.toFpDq(i).valid || io.toLsDq(i).valid
     io.recv(i) := (enq_ready(i) && enq_valid(i)) || cancelled(i)
-    when (io.recv(i) && !cancelled(i)) {
-      printf("[Cycle:%d][Dispatch1] instruction 0x%x accepted by queue %x %x %x\n",
-        GTimer(), io.fromRename(i).bits.cf.pc, io.toIntDq(i).valid, io.toFpDq(i).valid, io.toLsDq(i).valid)
-    }
-    when (io.recv(i) && cancelled(i)) {
-      printf("[Cycle:%d][Dispatch1] instruction 0x%x with brMask %x brTag %x cancelled\n",
-        GTimer(), io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.brMask, io.redirect.bits.brTag)
-    }
+    XSInfo(io.recv(i) && !cancelled(i), "instruction 0x%x accepted by queue %x %x %x\n",
+      io.fromRename(i).bits.cf.pc, io.toIntDq(i).valid, io.toFpDq(i).valid, io.toLsDq(i).valid)
+    XSInfo(io.recv(i) && cancelled(i), "instruction 0x%x with brMask %x brTag %x cancelled\n",
+      io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.brMask, io.redirect.bits.brTag)
   }
 
   // latch indexes from roq in case of DQ not fire
@@ -62,13 +58,13 @@ class Dispatch1 extends XSModule{
     when (io.toRoq(i).fire() && !io.recv(i)) {
       roqIndexReg(i) := io.roqIdxs(i)
       roqIndexRegValid(i) := true.B
-      printf("[Cycle:%d][Dispatch1] instruction 0x%x receives nboq %x but not accepted by queue (and it waits)\n",
-        GTimer(), io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
     }
     .elsewhen (io.recv(i)) {
       roqIndexRegValid(i) := false.B
-      printf("[Cycle:%d][Dispatch1] waiting instruction 0x%x is accepted by queue\n", GTimer(), io.fromRename(i).bits.cf.pc)
     }
+    XSDebug(io.toRoq(i).fire() && !io.recv(i),
+      "instruction 0x%x receives nboq %x but not accepted by queue (and it waits)\n",
+      io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
   }
 
   // append nroq to uop
@@ -76,9 +72,7 @@ class Dispatch1 extends XSModule{
   for (i <- 0 until RenameWidth) {
     uop_nroq(i) := io.fromRename(i).bits
     uop_nroq(i).roqIdx := Mux(io.toRoq(i).ready, io.roqIdxs(i), roqIndexReg(i))
-    when (io.toRoq(i).fire()) {
-      printf("[Cycle:%d][Dispatch1] instruction 0x%x receives nroq %d\n", GTimer(), io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
-    }
+    XSDebug(io.toRoq(i).fire(), "instruction 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
   }
 
   // uop can enqueue when rename.valid and roq.valid
@@ -100,9 +94,7 @@ class Dispatch1 extends XSModule{
     io.toRoq(i).bits <> io.fromRename(i).bits
     io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i)
     io.fromRename(i).ready := all_recv
-    when (io.fromRename(i).valid) {
-      printf("[Cycle:%d][Dispatch1] instruction 0x%x of type %b is in %d-th slot\n",
-        GTimer(), io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.ctrl.fuType, i.U)
-    }
+    XSDebug(io.fromRename(i).valid, "instruction 0x%x of type %b is in %d-th slot\n",
+      io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.ctrl.fuType, i.U)
   }
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.backend.regfile.RfReadPort
-import xiangshan.utils.GTimer
+import xiangshan.utils.{XSDebug, XSInfo}
 
 class Dispatch2 extends XSModule with NeedImpl {
   val io = IO(new Bundle() {
@@ -59,7 +59,7 @@ class Dispatch2 extends XSModule with NeedImpl {
     (uop.bits.ctrl.fuType === FuType.fmisc && i.U > fmisc0InstIdx) || uop.bits.ctrl.fuType === FuType.fmiscDivSqrt
   }) :+ true.B)
 
-  // TODO: currently there's only one LSU
+  // TODO: currently there's only one load/store reservation station
   // val load0InstIdx = PriorityEncoder(io.fromLsDq.map(deq => (deq.bits.ctrl.fuType === FuType.ldu)) :+ true.B)
   val load0InstIdx = PriorityEncoder(io.fromLsDq.map(deq => FuType.isMemExu(deq.bits.ctrl.fuType)) :+ true.B)
   val load1InstIdx = PriorityEncoder((io.fromLsDq.zipWithIndex map { case (uop, i) =>
@@ -93,25 +93,31 @@ class Dispatch2 extends XSModule with NeedImpl {
   // insert into reservation station
   val instIdxes = Seq(bruInstIdx, alu0InstIdx, alu1InstIdx, alu2InstIdx, alu3InstIdx, mulInstIdx, muldivInstIdx,
     fmac0InstIdx, fmac1InstIdx, fmac2InstIdx, fmac3InstIdx, fmisc0InstIdx, fmisc1InstIdx,
-    load0InstIdx, store0InstIdx)
+    load0InstIdx)//, store0InstIdx)
   io.enqIQCtrl.zipWithIndex map { case (enq, i) =>
     if (i < exuConfig.IntExuCnt) {
       enq.valid := !instIdxes(i)(2) && io.fromIntDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromIntDq(instIdxes(i)(1, 0)).bits
+      enq.bits.src1State := io.intPregRdy((instIdxes(i) << 1).asUInt())
+      enq.bits.src2State := io.intPregRdy((instIdxes(i) << 1).asUInt() + 1.U)
     }
     else if (i < exuConfig.IntExuCnt + exuConfig.FpExuCnt) {
       enq.valid := !instIdxes(i)(2) && io.fromFpDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromFpDq(instIdxes(i)(1, 0)).bits
+      enq.bits.src1State := io.fpPregRdy(instIdxes(i) * 3.U)
+      enq.bits.src2State := io.fpPregRdy(instIdxes(i) * 3.U + 1.U)
+      enq.bits.src3State := io.fpPregRdy(instIdxes(i) * 3.U + 2.U)
     }
     else {
       enq.valid := !instIdxes(i)(2) && io.fromLsDq(instIdxes(i)(1, 0)).valid
       enq.bits := io.fromLsDq(instIdxes(i)(1, 0)).bits
+      // TODO load and store
+      enq.bits.src1State := Mux(enq.bits.ctrl.fuType === FuType.ldu, io.intPregRdy(8), io.intPregRdy(10))
+      enq.bits.src2State := io.intPregRdy(11)
     }
 
-    when (enq.fire()) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x with type %b enters reservation station %d from %d\n",
-        GTimer(), enq.bits.cf.pc, enq.bits.ctrl.fuType, i.U, instIdxes(i))
-    }
+    XSInfo(enq.fire(), "instruction 0x%x with type %b enters reservation station %d from %d\n",
+      enq.bits.cf.pc, enq.bits.ctrl.fuType, i.U, instIdxes(i))
   }
 
   // responds to dispatch queue
@@ -119,42 +125,33 @@ class Dispatch2 extends XSModule with NeedImpl {
     io.fromIntDq(i).ready := (io.enqIQCtrl.zipWithIndex map {case (rs, j) =>
       (rs.ready && instIdxes(j) === i.U && (j < exuConfig.IntExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    when (io.fromIntDq(i).fire()) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x leaves Int dispatch queue with nroq %d\n",
-        GTimer(), io.fromIntDq(i).bits.cf.pc, io.fromIntDq(i).bits.roqIdx)
-    }
-    when (io.fromIntDq(i).valid && !io.fromIntDq(i).ready) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x waits at Int dispatch queue with index %d\n",
-        GTimer(), io.fromIntDq(i).bits.cf.pc, i.U)
-    }
+    XSInfo(io.fromIntDq(i).fire(), "instruction 0x%x leaves Int dispatch queue with nroq %d\n",
+      io.fromIntDq(i).bits.cf.pc, io.fromIntDq(i).bits.roqIdx)
+    XSDebug(io.fromIntDq(i).valid && !io.fromIntDq(i).ready,
+      "instruction 0x%x waits at Int dispatch queue with index %d\n",
+      io.fromIntDq(i).bits.cf.pc, i.U)
   }
   for (i <- 0 until FpDqDeqWidth) {
     io.fromFpDq(i).ready := (io.enqIQCtrl.zipWithIndex map {case (rs, j) =>
       (rs.ready && instIdxes(j) === i.U
         && (j >= exuConfig.IntExuCnt && j < exuConfig.IntExuCnt + exuConfig.FpExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    when (io.fromFpDq(i).fire()) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x leaves Fp dispatch queue with nroq %d\n",
-        GTimer(), io.fromFpDq(i).bits.cf.pc, io.fromFpDq(i).bits.roqIdx)
-    }
-    when (io.fromFpDq(i).valid && !io.fromFpDq(i).ready) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x waits at Fp dispatch queue with index %d\n",
-        GTimer(), io.fromFpDq(i).bits.cf.pc, i.U)
-    }
+    XSInfo(io.fromFpDq(i).fire(), "instruction 0x%x leaves Fp dispatch queue with nroq %d\n",
+      io.fromFpDq(i).bits.cf.pc, io.fromFpDq(i).bits.roqIdx)
+    XSDebug(io.fromFpDq(i).valid && !io.fromFpDq(i).ready,
+      "instruction 0x%x waits at Fp dispatch queue with index %d\n",
+      io.fromFpDq(i).bits.cf.pc, i.U)
   }
   for (i <- 0 until LsDqDeqWidth) {
     io.fromLsDq(i).ready := (io.enqIQCtrl.zipWithIndex map {case (rs, j) =>
       (rs.ready && instIdxes(j) === i.U
         && (j >= exuConfig.IntExuCnt + exuConfig.FpExuCnt).asBool())
     }).reduce((l, r) => l || r)
-    when (io.fromLsDq(i).fire()) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x leaves Ls dispatch queue with nroq %d\n",
-        GTimer(), io.fromLsDq(i).bits.cf.pc, io.fromLsDq(i).bits.roqIdx)
-    }
-    when (io.fromLsDq(i).valid && !io.fromLsDq(i).ready) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x waits at Ls dispatch queue with index %d\n",
-        GTimer(), io.fromLsDq(i).bits.cf.pc, i.U)
-    }
+    XSInfo(io.fromLsDq(i).fire(), "instruction 0x%x leaves Ls dispatch queue with nroq %d\n",
+      io.fromLsDq(i).bits.cf.pc, io.fromLsDq(i).bits.roqIdx)
+    XSDebug(io.fromLsDq(i).valid && !io.fromLsDq(i).ready,
+      "instruction 0x%x waits at Ls dispatch queue with index %d\n",
+      io.fromLsDq(i).bits.cf.pc, i.U)
   }
 
   // next stage: insert data
@@ -207,12 +204,12 @@ class Dispatch2 extends XSModule with NeedImpl {
 
     io.enqIQData(i).valid := data_valid(i)
     io.enqIQData(i).bits.uop := uop_reg(i)
-    io.enqIQData(i).bits.uop.src1State := Mux(src1Type(i)(1), SrcState.rdy,
-      Mux(src1Type(i)(0), io.intPregRdy(src1Index(i)), io.fpPregRdy(src1Index(i))))
-    io.enqIQData(i).bits.uop.src2State := Mux(src2Type(i)(1), SrcState.rdy,
-      Mux(src2Type(i)(0), io.intPregRdy(src2Index(i)), io.fpPregRdy(src2Index(i))))
-    io.enqIQData(i).bits.uop.src3State := Mux(src3Type(i)(1), SrcState.rdy,
-      Mux(src3Type(i)(0), io.intPregRdy(src3Index(i)), io.fpPregRdy(src3Index(i))))
+//    io.enqIQData(i).bits.uop.src1State := Mux(src1Type(i)(1), SrcState.rdy,
+//      Mux(src1Type(i)(0), io.intPregRdy(src1Index(i)), io.fpPregRdy(src1Index(i))))
+//    io.enqIQData(i).bits.uop.src2State := Mux(src2Type(i)(1), SrcState.rdy,
+//      Mux(src2Type(i)(0), io.intPregRdy(src2Index(i)), io.fpPregRdy(src2Index(i))))
+//    io.enqIQData(i).bits.uop.src3State := Mux(src3Type(i)(1), SrcState.rdy,
+//      Mux(src3Type(i)(0), io.intPregRdy(src3Index(i)), io.fpPregRdy(src3Index(i))))
     val src1 = Mux(src1Type(i)(1), 0.U,
       Mux(src1Type(i)(0), io.readFpRf(src1Index(i)).data, io.readIntRf(src1Index(i)).data))
     io.enqIQData(i).bits.src1 := Mux(index_reg(i)(2), 0.U, src1)
@@ -223,11 +220,10 @@ class Dispatch2 extends XSModule with NeedImpl {
       Mux(src3Type(i)(0), io.readFpRf(src3Index(i)).data, io.readIntRf(src3Index(i)).data))
     io.enqIQData(i).bits.src3 := Mux(index_reg(i)(2), 0.U, src3)
 
-    when (io.enqIQData(i).valid) {
-      printf("[Cycle:%d][Dispatch2] instruction 0x%x reads operands from (%d, %d, %x), (%d, %d, %x), (%d, %d, %x)\n",
-        GTimer(), io.enqIQData(i).bits.uop.cf.pc,
-        src1Type(i), src1Index(i), src1, src2Type(i), src2Index(i), src2, src3Type(i), src3Index(i), src3)
-    }
+    XSDebug(io.enqIQData(i).valid,
+      "instruction 0x%x reads operands from (%d, %d, %x), (%d, %d, %x), (%d, %d, %x)\n",
+      io.enqIQData(i).bits.uop.cf.pc, src1Type(i), src1Index(i), src1,
+      src2Type(i), src2Index(i), src2, src3Type(i), src3Index(i), src3)
   }
 
 }

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -2,7 +2,7 @@ package xiangshan.backend.dispatch
 
 import chisel3._
 import chisel3.util._
-import xiangshan.utils.GTimer
+import xiangshan.utils.{XSDebug, XSInfo}
 import xiangshan.{MicroOp, Redirect, XSBundle, XSModule}
 
 
@@ -61,9 +61,10 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, name: String) extends X
   for (i <- 0 until size) {
     when (cancelled(i) && entriesValid(i)) {
       entriesValid(i) := false.B
-      printf("[Cycle:%d][" + name + "] valid entry(%d)(pc = %x) cancelled with brMask %x brTag %x\n",
-        GTimer(), i.U, entries(i).cf.pc, entries(i).brMask, io.redirect.bits.brTag)
     }
+    XSInfo(cancelled(i) && entriesValid(i),
+      name + ": valid entry(%d)(pc = %x) cancelled with brMask %x brTag %x\n",
+      i.U, entries(i).cf.pc, entries(i).brMask, io.redirect.bits.brTag)
   }
 
   // enqueue
@@ -87,16 +88,10 @@ class DispatchQueue(size: Int, enqnum: Int, deqnum: Int, name: String) extends X
   head := (head + num_deq) % size.U
   head_direction := ((Cat(0.U(1.W), head) + num_deq) >= size.U).asUInt() ^ head_direction
 
-  when (num_deq > 0.U) {
-    printf("[Cycle:%d][" + name + "] num_deq = %d, head = (%d -> %d)\n",
-      GTimer(), num_deq, head, (head + num_deq) % size.U)
-  }
-  when (num_enq > 0.U) {
-    printf("[Cycle:%d][" + name + "] num_enq = %d, tail = (%d -> %d)\n",
-      GTimer(), num_enq, tail, (tail + num_enq) % size.U)
-  }
-  when (valid_entries > 0.U) {
-    printf("[Cycle:%d][" + name + "] valid_entries = %d, head = (%d, %d), tail = (%d, %d), \n",
-      GTimer(), valid_entries, head_direction, head, tail_direction, tail)
-  }
+  XSDebug(num_deq > 0.U, name + ": num_deq = %d, head = (%d -> %d)\n",
+      num_deq, head, (head + num_deq) % size.U)
+  XSDebug(num_enq > 0.U, name + "] num_enq = %d, tail = (%d -> %d)\n",
+      num_enq, tail, (tail + num_enq) % size.U)
+  XSDebug(valid_entries > 0.U, name + "] valid_entries = %d, head = (%d, %d), tail = (%d, %d), \n",
+      valid_entries, head_direction, head, tail_direction, tail)
 }
\ No newline at end of file

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -24,7 +24,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
 
   val exuData = Reg(Vec(RoqSize, UInt(XLEN.W)))//for debug
   val exuDebug = Reg(Vec(RoqSize, new DebugBundle))//for debug
-  val archRF = RegInit(VecInit(List.fill(32)(0.U(32.W))))//for debug
+  val archRF = RegInit(VecInit(List.fill(64)(0.U(32.W))))//for debug, fp regs included
 
   val ringBufferHeadExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))
   val ringBufferTailExtended = RegInit(0.U(ExtendedRoqIdxWidth.W))

src/main/scala/xiangshan/utils/LogUtils.scala

@@ -18,7 +18,7 @@ object XSLogLevel extends Enumeration {
 object XSLog extends HasXSParameter{
   def apply(debugLevel: XSLogLevel)
            (cond: Bool, pable: Printable)
-           (implicit m: Module = null): Any = {
+           (implicit m: Module): Any = {
     if (debugLevel >= LogLevel) {
       when (cond) {
         val commonInfo = p"[$debugLevel][time=${GTimer()}] ${m.name}: "
@@ -28,12 +28,18 @@ object XSLog extends HasXSParameter{
   }
 }
 
-sealed abstract class LogHelper(val logLevel: XSLogLevel) {
+sealed abstract class LogHelper(val logLevel: XSLogLevel) extends HasXSParameter {
 
   def apply(cond: Bool, fmt: String, data: Bits*)(implicit m: Module): Any =
     apply(cond, Printable.pack(fmt, data:_*))
-
   def apply(cond: Bool, pable: Printable)(implicit m: Module): Any = XSLog(logLevel)(cond, pable)
+  def apply(fmt: String, data: Bits*)(implicit m: Module): Any =
+    apply(true.B, Printable.pack(fmt, data:_*))
+  def apply(pable: Printable)(implicit m: Module): Any = XSLog(logLevel)(true.B, pable)
+
+  // Do not use that unless you have valid reasons
+  def apply(cond: Bool = true.B)(body: => Unit): Any =
+    if (logLevel >= LogLevel) { when (cond) { body } }
 }
 
 object XSDebug extends LogHelper(XSLogLevel.DEBUG)

src/test/csrc/difftest.cpp

@@ -86,7 +86,7 @@ static const char *reg_name[DIFFTEST_NR_REG] = {
 int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
   int skip, int isRVC, uint64_t intrNO, int priviledgeMode) {
 
-  assert(!skip && !isRVC && intrNO == 0)
+  assert(!skip && !isRVC && intrNO == 0);
   #define DEBUG_RETIRE_TRACE_SIZE 16
 
   uint64_t ref_r[DIFFTEST_NR_REG];
@@ -116,7 +116,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
     ref_difftest_exec(1);//TODO
   }
 
-  assert(commit > 0 && commit <= 6)
+  assert(commit > 0 && commit <= 6);
   ref_difftest_exec(commit);
   ref_difftest_getregs(&ref_r);
 

src/test/scala/top/XSSim.scala

@@ -11,10 +11,10 @@ import xiangshan._
 
 class DiffTestIO extends Bundle {
   val r = Output(Vec(64, UInt(64.W)))
-  val commit = Output(Bool())
+  val commit = Output(UInt(32.W))
   val thisPC = Output(UInt(64.W))
   val thisINST = Output(UInt(32.W))
-  val isMMIO = Output(Bool())
+  val skip = Output(Bool())
   val isRVC = Output(Bool())
   val intrNO = Output(UInt(64.W))
   
@@ -54,7 +54,7 @@ class XSSimTop extends Module {
   BoringUtils.addSink(difftest.commit, "difftestCommit")
   BoringUtils.addSink(difftest.thisPC, "difftestThisPC")
   BoringUtils.addSink(difftest.thisINST, "difftestThisINST")
-  BoringUtils.addSink(difftest.isMMIO, "difftestIsMMIO")
+  BoringUtils.addSink(difftest.skip, "difftestSkip")
   BoringUtils.addSink(difftest.isRVC, "difftestIsRVC")
   BoringUtils.addSink(difftest.intrNO, "difftestIntrNO")
   BoringUtils.addSink(difftest.r, "difftestRegs")