From 3665ef3092bc014364758736f7bd0abaee23d126 Mon Sep 17 00:00:00 2001 From: Jay Date: Wed, 1 Dec 2021 13:25:59 +0800 Subject: [PATCH] ICacheMainPipe: fix a bug in set conflict (#1284) --- src/main/scala/xiangshan/frontend/icache/ICache.scala | 2 +- src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/icache/ICache.scala b/src/main/scala/xiangshan/frontend/icache/ICache.scala index 0011e925e..5f84cd89a 100644 --- a/src/main/scala/xiangshan/frontend/icache/ICache.scala +++ b/src/main/scala/xiangshan/frontend/icache/ICache.scala @@ -556,7 +556,7 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame val fetchShouldBlock = VecInit(fetchReq.map(req => VecInit(hasMiss.zip(missSetSeq).map{case(valid, idx)=> valid && idx === req.bits.vsetIdx}).reduce(_||_))) (0 until PortNumber).map{i => - mainpipe.io.fetch(i).req.valid := io.fetch(i).req.valid && !fetchShouldBlock(i) + mainpipe.io.fetch(i).req.valid := io.fetch(i).req.valid //&& !fetchShouldBlock(i) io.fetch(i).req.ready := mainpipe.io.fetch(i).req.ready && !fetchShouldBlock(i) mainpipe.io.fetch(i).req.bits := io.fetch(i).req.bits } diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala index fea2e2f14..c9de46287 100644 --- a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala +++ b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala @@ -139,7 +139,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule //fetch: send addr to Meta/TLB and Data simultaneously val fetch_req = List(toMeta, toData) for(i <- 0 until 2) { - fetch_req(i).valid := s0_fire + fetch_req(i).valid := s0_valid fetch_req(i).bits.isDoubleLine := s0_double_line fetch_req(i).bits.vSetIdx := s0_req_vsetIdx } @@ -550,7 +550,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule (0 until PortNumber).map{ i => io.setInfor.s2(i).valid := s2_bank_miss(i) && s2_valid - io.setInfor.s2(i).vidx := s1_req_vsetIdx(i) + io.setInfor.s2(i).vidx := s2_req_vsetIdx(i) } val miss_all_fix = wait_state === wait_finish -- GitLab