Merge pull request #67 from RISCVERS/debug-missing-brmask

Fix bugs, 4 insts retired successfully

src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala

@@ -23,5 +23,9 @@ class DecodeBuffer extends XSModule {
 
   q.io.flush := io.redirect.valid
   q.io.enq <> io.in
-  io.out <> q.io.deq
+  for((out, deq) <- io.out.zip(q.io.deq)){
+    out.bits := deq.bits
+    out.valid := deq.valid && !io.redirect.valid
+    deq.ready := out.ready
+  }
 }

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -16,6 +16,11 @@ class Decoder extends XSModule with HasInstrType {
     val in = Input(new CtrlFlow)
     val out = Output(new CfCtrl)
   })
+
+
+  io.out := DontCare // FIXME: remove me!!!
+  io.out.cf := io.in
+
   val hasIntr = Wire(Bool())
   val instr: UInt = io.in.instr
   val decodeList = ListLookup(instr, Instructions.DecodeDefault, Instructions.DecodeTable)
@@ -30,9 +35,6 @@ class Decoder extends XSModule with HasInstrType {
 //  val rvcImmType :: rvcSrc1Type :: rvcSrc2Type :: rvcDestType :: Nil =
 //    ListLookup(instr, CInstructions.DecodeDefault, CInstructions.CExtraDecodeTable)
 
-  io.out := DontCare
-
-  io.out.cf := io.in
   io.out.ctrl.fuOpType := fuOpType
   io.out.ctrl.fuType := fuType
 
@@ -149,12 +151,11 @@ class Decoder extends XSModule with HasInstrType {
 
   //output signals
 
-  io.out.cf <> io.in
-
 //  Debug(){
 //    when(io.out.fire()){printf("[IDU] issue: pc %x npc %x instr %x\n", io.out.bits.cf.pc, io.out.bits.cf.pnpc, io.out.bits.cf.instr)}
 //  }
 
+  //FIXME: move it to ROB
   val intrVec = WireInit(0.U(12.W))
   BoringUtils.addSink(intrVec, "intrVecIDU")
   io.out.cf.intrVec.zip(intrVec.asBools).map{ case(x, y) => x := y }

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -32,6 +32,7 @@ class Dispatch1 extends XSModule{
   val cancelled = Wire(Vec(RenameWidth, Bool()))
   for (i <- 0 until RenameWidth) {
     cancelled(i) := ((io.fromRename(i).bits.brMask & UIntToOH(io.redirect.bits.brTag)) =/= 0.U) && io.redirect.valid
+    XSDebug(io.redirect.valid, p"pc=${Hexadecimal(io.fromRename(i).bits.cf.pc)} brMask:${Binary(io.fromRename(i).bits.brMask)} brTag:${io.redirect.bits.brTag}\n")
   }
 
   // enqueue handshake
@@ -91,7 +92,7 @@ class Dispatch1 extends XSModule{
   val all_recv = recv_vector.reduce((x, y) => x && y).asBool()
   for (i <- 0 until RenameWidth) {
     io.toRoq(i).bits <> io.fromRename(i).bits
-    io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i)
+    io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i) && !cancelled(i)
     XSDebug(io.toRoq(i).fire(), "instruction 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
     if (i > 0) {
       XSWarn(io.toRoq(i).fire() && !io.toRoq(i - 1).ready && io.toRoq(i - 1).valid,

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -210,16 +210,13 @@ class Dispatch2 extends XSModule {
 //      Mux(src2Type(i)(0), io.intPregRdy(src2Index(i)), io.fpPregRdy(src2Index(i))))
 //    io.enqIQData(i).bits.uop.src3State := Mux(src3Type(i)(1), SrcState.rdy,
 //      Mux(src3Type(i)(0), io.intPregRdy(src3Index(i)), io.fpPregRdy(src3Index(i))))
-    val src1 = Mux(src1Type(i)(1), 0.U,
-      Mux(src1Type(i)(0), io.readFpRf(src1Index(i)).data, io.readIntRf(src1Index(i)).data))
+    val src1 = Mux(src1Type(i)(1), io.readFpRf(src1Index(i)).data, io.readIntRf(src1Index(i)).data)
     io.enqIQData(i).bits.src1 := Mux(io.enqIQData(i).bits.uop.ctrl.src1Type === SrcType.pc,
         io.enqIQData(i).bits.uop.cf.pc, Mux(index_reg(i)(2), 0.U, src1))
-    val src2 = Mux(src2Type(i)(1), 0.U,
-      Mux(src2Type(i)(0), io.readFpRf(src2Index(i)).data, io.readIntRf(src2Index(i)).data))
-    io.enqIQData(i).bits.src2 := Mux(io.enqIQData(i).bits.uop.ctrl.src1Type === SrcType.imm,
+    val src2 = Mux(src2Type(i)(1), io.readFpRf(src2Index(i)).data, io.readIntRf(src2Index(i)).data)
+    io.enqIQData(i).bits.src2 := Mux(io.enqIQData(i).bits.uop.ctrl.src2Type === SrcType.imm,
       io.enqIQData(i).bits.uop.ctrl.imm, Mux(index_reg(i)(2), 0.U, src2))
-    val src3 = Mux(src3Type(i)(1), 0.U,
-      Mux(src3Type(i)(0), io.readFpRf(src3Index(i)).data, io.readIntRf(src3Index(i)).data))
+    val src3 = Mux(src3Type(i)(1), io.readFpRf(src3Index(i)).data, io.readIntRf(src3Index(i)).data)
     io.enqIQData(i).bits.src3 := Mux(index_reg(i)(2), 0.U, src3)
 
     XSDebug(io.enqIQData(i).valid,

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.rename
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import xiangshan.utils.XSInfo
+import xiangshan.utils.{ParallelOR, XSInfo}
 
 class Rename extends XSModule {
   val io = IO(new Bundle() {
@@ -21,8 +21,10 @@ class Rename extends XSModule {
     val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
   })
 
+  val isWalk = ParallelOR(io.roqCommits.map(x => x.valid && x.bits.isWalk)).asBool()
+
   val debug_exception = io.redirect.valid && io.redirect.bits.isException
-  val debug_walk = io.roqCommits.map(_.bits.isWalk).reduce(_ || _)
+  val debug_walk = isWalk
   val debug_norm = !(debug_exception || debug_walk)
 
   def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = {
@@ -62,8 +64,8 @@ class Rename extends XSModule {
   val uops = Wire(Vec(RenameWidth, new MicroOp))
 
   uops.foreach( uop => {
-    uop.brMask := DontCare
-    uop.brTag := DontCare
+//    uop.brMask := DontCare
+//    uop.brTag := DontCare
     uop.src1State := DontCare
     uop.src2State := DontCare
     uop.src3State := DontCare
@@ -71,19 +73,23 @@ class Rename extends XSModule {
   })
 
   var last_can_alloc = WireInit(true.B)
-  for(i <- 0 until RenameWidth){
+  for(i <- 0 until RenameWidth) {
     uops(i).cf := io.in(i).bits.cf
     uops(i).ctrl := io.in(i).bits.ctrl
+    uops(i).brMask := io.in(i).bits.brMask
+    uops(i).brTag := io.in(i).bits.brTag
+
+    val inValid = io.in(i).valid && !isWalk
 
     // alloc a new phy reg
-    val needFpDest = io.in(i).valid && needDestReg(fp = true, io.in(i).bits)
-    val needIntDest = io.in(i).valid && needDestReg(fp = false, io.in(i).bits)
+    val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits)
+    val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits)
     fpFreeList.allocReqs(i) := needFpDest && last_can_alloc && io.out(i).ready
     intFreeList.allocReqs(i) := needIntDest && last_can_alloc && io.out(i).ready
     val fpCanAlloc = fpFreeList.canAlloc(i)
     val intCanAlloc = intFreeList.canAlloc(i)
     val this_can_alloc = Mux(needIntDest, intCanAlloc, fpCanAlloc)
-    io.in(i).ready := this_can_alloc
+    io.in(i).ready := this_can_alloc && !isWalk
     last_can_alloc = last_can_alloc && this_can_alloc
     uops(i).pdest := Mux(needIntDest, intFreeList.pdests(i), fpFreeList.pdests(i))
     uops(i).freelistAllocPtr := Mux(needIntDest, intFreeList.allocPtrs(i), fpFreeList.allocPtrs(i))
@@ -107,7 +113,7 @@ class Rename extends XSModule {
       rat.specWritePorts(i).wdata := Mux(specWen, freeList.pdests(i), io.roqCommits(i).bits.uop.old_pdest)
 
       XSInfo(walkWen,
-        {if(fp) "fp" else "int "} + p"walk: pc:${Hexadecimal(uops(i).cf.pc)}" +
+        {if(fp) p"fp" else p"int "} + p"walk: pc:${Hexadecimal(uops(i).cf.pc)}" +
           p" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
       )
 
@@ -116,7 +122,7 @@ class Rename extends XSModule {
       rat.archWritePorts(i).wdata := io.roqCommits(i).bits.uop.pdest
 
       XSInfo(rat.archWritePorts(i).wen,
-        {if(fp) "fp" else "int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
+        {if(fp) p"fp" else p"int "} + p" rat arch: ldest:${rat.archWritePorts(i).addr}" +
           p" pdest:${rat.archWritePorts(i).wdata}\n"
       )
 

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -118,7 +118,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
         i.U, ringBufferTail+i.U, microOp(ringBufferTail+i.U).cf.pc)
   }
 
-  val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_)
+  //TODO: add walkFin Vec, io.commits(i).valid depends on it
+  val walkFinished = (0 until CommitWidth).map(i => (ringBufferWalk + i.U) === ringBufferWalkTarget).reduce(_||_) //FIXIT!!!!!!
 
   when(state===s_walk) {
     //exit walk state when all roq entry is commited
@@ -129,11 +130,12 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     XSInfo("rolling back: head %d tail %d walk %d\n", ringBufferHead, ringBufferTail, ringBufferWalk)
   }
 
+  val newHead = io.brqRedirect.bits.roqIdx + 1.U
   when(io.brqRedirect.valid){
     state := s_walk
-    ringBufferWalkExtended := io.brqRedirect.bits.roqIdx
+    ringBufferWalkExtended := newHead
     ringBufferWalkTarget := ringBufferHeadExtended
-    ringBufferHeadExtended := io.brqRedirect.bits.roqIdx
+    ringBufferHeadExtended := newHead
   }
 
   // roq redirect only used for exception