@@ -95,6 +95,12 @@ class Roq(implicit val p: XSConfig) extends XSModule {
}
io.commits(i).bits.isWalk:=state===s_walk
}
for(i<-0untilCommitWidth){
XSInfo(io.commits(i).valid&&state=/=s_walk,"retired pc %x wen %d ldst %d data %x\n",microOp(ringBufferTail+i.U).cf.pc,microOp(ringBufferTail+i.U).ctrl.rfWen,microOp(ringBufferTail+i.U).ctrl.ldest,exuData(ringBufferTail+i.U))
}
for(i<-0untilCommitWidth){
XSInfo(io.commits(i).valid&&state===s_walk,"walked pc %x wen %d ldst %d data %x\n",microOp(ringBufferTail+i.U).cf.pc,microOp(ringBufferTail+i.U).ctrl.rfWen,microOp(ringBufferTail+i.U).ctrl.ldest,exuData(ringBufferTail+i.U))