Merge pull request #66 from RISCVERS/dev-difftest

Fix difftest

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -65,20 +65,20 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   }
 
   // Writeback
+  val firedWriteback = VecInit((0 until exuConfig.ExuCnt).map(io.exeWbResults(_).fire())).asUInt
+  XSInfo(PopCount(firedWriteback) > 0.U, "writebacked %d insts\n", PopCount(firedWriteback))
   for(i <- 0 until exuConfig.ExuCnt){
     when(io.exeWbResults(i).fire()){
       writebacked(io.exeWbResults(i).bits.uop.roqIdx) := true.B
       exuData(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.data
       exuDebug(io.exeWbResults(i).bits.uop.roqIdx) := io.exeWbResults(i).bits.debug
-      XSInfo("0x%x writebacks 0x%x\n", io.exeWbResults(i).bits.uop.cf.pc, io.exeWbResults(i).bits.data)
+      XSInfo(io.exeWbResults(i).valid, "writebacked pc 0x%x wen %d data 0x%x\n", 
+        microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc,
+        microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, 
+        io.exeWbResults(i).bits.data
+      )
     }
   }
-  val firedWriteback = VecInit((0 until exuConfig.ExuCnt).map(io.exeWbResults(_).fire())).asUInt
-  XSInfo(PopCount(firedWriteback) > 0.U, "writebacked %d insts\n", PopCount(firedWriteback))
-  for(i <- 0 until exuConfig.ExuCnt){
-    XSInfo(io.exeWbResults(i).valid, "writebacked pc 0x%x wen %d data 0x%x\n", microOp(io.exeWbResults(i).bits.uop.roqIdx).cf.pc,
-      microOp(io.exeWbResults(i).bits.uop.roqIdx).ctrl.rfWen, io.exeWbResults(i).bits.data)
-  }
 
   // Commit uop to Rename
   for(i <- 0 until CommitWidth){
@@ -86,7 +86,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
       val canCommit = if(i!=0) io.commits(i-1).valid else true.B
       io.commits(i).valid := valid(ringBufferTail+i.U) && writebacked(ringBufferTail+i.U) && canCommit
       io.commits(i).bits.uop := microOp(ringBufferTail+i.U)
-      when(microOp(ringBufferTail+i.U).ctrl.rfWen){ archRF(microOp(ringBufferTail+i.U).ctrl.ldest) := exuData(ringBufferTail+i.U) }
+      when(io.commits(i).valid && microOp(ringBufferTail+i.U).ctrl.rfWen){ archRF(microOp(ringBufferTail+i.U).ctrl.ldest) := exuData(ringBufferTail+i.U) }
       when(io.commits(i).valid){valid(ringBufferTail+i.U) := false.B}
     }.otherwise{//state === s_walk
       io.commits(i).valid := valid(ringBufferWalk+i.U) && writebacked(ringBufferWalk+i.U)
@@ -95,6 +95,12 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     }
     io.commits(i).bits.isWalk := state === s_walk
   }
+  for(i <- 0 until CommitWidth){
+    XSInfo(io.commits(i).valid && state =/= s_walk, "retired pc %x wen %d ldst %d data %x\n", microOp(ringBufferTail+i.U).cf.pc, microOp(ringBufferTail+i.U).ctrl.rfWen, microOp(ringBufferTail+i.U).ctrl.ldest, exuData(ringBufferTail+i.U))
+  }
+  for(i <- 0 until CommitWidth){
+    XSInfo(io.commits(i).valid && state === s_walk, "walked pc %x wen %d ldst %d data %x\n", microOp(ringBufferTail+i.U).cf.pc, microOp(ringBufferTail+i.U).ctrl.rfWen, microOp(ringBufferTail+i.U).ctrl.ldest, exuData(ringBufferTail+i.U))
+  }
 
   val validCommit = VecInit((0 until CommitWidth).map(i => io.commits(i).valid)).asUInt
   when(state === s_idle){

src/test/csrc/difftest.cpp

@@ -96,6 +96,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
   static uint64_t nemu_this_pc = 0x80000000;
   static uint64_t pc_retire_queue[DEBUG_RETIRE_TRACE_SIZE] = {0};
   static uint32_t inst_retire_queue[DEBUG_RETIRE_TRACE_SIZE] = {0};
+  static uint32_t retire_cnt_queue[DEBUG_RETIRE_TRACE_SIZE] = {0};
   static int pc_retire_pointer = 7;
 
   if (skip) {
@@ -108,6 +109,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
     pc_retire_pointer = (pc_retire_pointer+1) % DEBUG_RETIRE_TRACE_SIZE;
     pc_retire_queue[pc_retire_pointer] = this_pc;
     inst_retire_queue[pc_retire_pointer] = this_inst;
+    retire_cnt_queue[pc_retire_pointer] = commit;
     return 0;
   }
 
@@ -124,6 +126,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
   pc_retire_pointer = (pc_retire_pointer+1) % DEBUG_RETIRE_TRACE_SIZE;
   pc_retire_queue[pc_retire_pointer] = this_pc;
   inst_retire_queue[pc_retire_pointer] = this_inst;
+  retire_cnt_queue[pc_retire_pointer] = commit;
   
   // TODO: fix mip.mtip
   // int isCSR = ((this_inst & 0x7f) ==  0x73);
@@ -146,7 +149,7 @@ int difftest_step(int commit, uint64_t *reg_scala, uint32_t this_inst,
     printf("\n==============Retire Trace==============\n");
     int j;
     for(j = 0; j < DEBUG_RETIRE_TRACE_SIZE; j++){
-      printf("retire trace [%x]: pc %010lx inst %08x %s\n", j, pc_retire_queue[j], inst_retire_queue[j], (j==pc_retire_pointer)?"<--":"");
+      printf("retire trace [%x]: pc %010lx inst %08x cmtcnt %d %s\n", j, pc_retire_queue[j], inst_retire_queue[j], retire_cnt_queue[j], (j==pc_retire_pointer)?"<--":"");
     }
     printf("\n==============  Reg Diff  ==============\n");
     ref_isa_reg_display();